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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.
16
H8/36049Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series H8/36049F H8/36049 H8/36048 H8/36047 HD64F36049, HD64F36049G, HD64336049, HD64336049G, HD64336048, HD64336048G, HD64336047, HD64336047G
Rev.3.00 Revision Date: Mar. 15, 2006
Rev. 3.00 Mar. 15, 2006 Page ii of xxxii
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
Rev. 3.00 Mar. 15, 2006 Page iii of xxxii
General Precautions on Handling of Product
1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed.
Rev. 3.00 Mar. 15, 2006 Page iv of xxxii
Configuration of This Manual
This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index
Rev. 3.00 Mar. 15, 2006 Page v of xxxii
Preface
The H8/36049 Group comprises single-chip microcomputers made up of the high-speed H8/300H CPU as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible with the H8/300 CPU. Target Users: This manual was written for users who will be using the H8/36049 Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8/36049 Group to the target users. Refer to the H8/300H Series Software Manual for a detailed description of the instruction set.
Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the H8/300H Series Software Manual. * In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 22, List of Registers. Example: The following notation is used for cases when the same or a similar function, e.g. serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB is on the left and the LSB is on the right. Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, and decimal is xxxx. Signal notation: An overbar is added to a low-active signal: xxxx Register name:
Rev. 3.00 Mar. 15, 2006 Page vi of xxxii
Notes: When using an on-chip emulator (E7 or E8) for H8/36049 Group program development and debugging, the following restrictions must be noted. The NMI pin is reserved for the E7 or E8, and cannot be used. Pins P85, P86, and P87 cannot be used. Area H'FFF780 to H'FFFB7F must on no account be accessed. When the E7 or E8 is used, address breaks can be set as either available to the user or for use by the E7 or E8. If address breaks are set as being used by the E7 or E8, the address break control registers must not be accessed. 5. When the E7 or E8 is used, NMI is an input/output pin (open-drain in output mode), P85 and P87 are input pins, and P86 is an output pin. 6. In on-board programming mode by boot mode, channel 1 (P21/RXD and P22/TXD) for SCI3 is used. 1. 2. 3. 4. Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/
H8/36049 Group manuals:
Document Title H8/36049 Group Hardware Manual H8/300H Series Software Manual Document No. This manual REJ09B0213
User's manuals for development tools:
Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual H8S, H8/300 Series Simulator/Debugger User's Manual H8S, H8/300 Series High-performance Embedded Workshop 3 Tutorial Document No. REJ10B0058 REJ10B0211 REJ10B0024
H8S, H8/300 Series High-performance Embedded Workshop 3 User's Manual REJ10B0026
Rev. 3.00 Mar. 15, 2006 Page vii of xxxii
Application notes:
Document Title H8S, H8/300 Series C/C++ Compiler Package Application Note Single Power Supply F-ZTATTM On-Board Programming Document No. REJ05B0464 REJ05B0520
Rev. 3.00 Mar. 15, 2006 Page viii of xxxii
Contents
Section 1 Overview................................................................................................1
1.1 1.2 1.3 1.4 Features................................................................................................................................. 1 Internal Block Diagram......................................................................................................... 3 Pin Arrangement ................................................................................................................... 4 Pin Functions ........................................................................................................................ 5
Section 2 CPU........................................................................................................9
2.1 2.2 Address Space and Memory Map ....................................................................................... 10 Register Configuration........................................................................................................ 11 2.2.1 General Registers................................................................................................ 12 2.2.2 Program Counter (PC) ........................................................................................ 13 2.2.3 Condition-Code Register (CCR)......................................................................... 13 Data Formats....................................................................................................................... 15 2.3.1 General Register Data Formats ........................................................................... 15 2.3.2 Memory Data Formats ........................................................................................ 17 Instruction Set ..................................................................................................................... 18 2.4.1 List of Instructions Classified by Function ......................................................... 18 2.4.2 Basic Instruction Formats ................................................................................... 27 Addressing Modes and Effective Address Calculation....................................................... 28 2.5.1 Addressing Modes .............................................................................................. 28 2.5.2 Effective Address Calculation ............................................................................ 31 Basic Bus Cycle .................................................................................................................. 33 2.6.1 Access to On-Chip Memory (RAM, ROM)........................................................ 33 2.6.2 On-Chip Peripheral Modules .............................................................................. 34 CPU States .......................................................................................................................... 35 Usage Notes ........................................................................................................................ 36 2.8.1 Notes on Data Access to Empty Areas ............................................................... 36 2.8.2 EEPMOV Instruction.......................................................................................... 36 2.8.3 Bit Manipulation Instruction............................................................................... 37
2.3
2.4
2.5
2.6
2.7 2.8
Section 3 Exception Handling .............................................................................43
3.1 3.2 Exception Sources and Vector Address .............................................................................. 44 Register Descriptions.......................................................................................................... 46 3.2.1 Interrupt Edge Select Register 1 (IEGR1) .......................................................... 47 3.2.2 Interrupt Edge Select Register 2 (IEGR2) .......................................................... 48 3.2.3 Interrupt Enable Register 1 (IENR1) .................................................................. 49
Rev. 3.00 Mar. 15, 2006 Page ix of xxxii
3.3 3.4
3.5
3.2.4 Interrupt Enable Register 2 (IENR2) .................................................................. 50 3.2.5 Interrupt Flag Register 1 (IRR1)......................................................................... 50 3.2.6 Interrupt Flag Register 2 (IRR2)......................................................................... 52 3.2.7 Wakeup Interrupt Flag Register (IWPR) ............................................................ 53 Reset Exception Handling .................................................................................................. 54 Interrupt Exception Handling ............................................................................................. 55 3.4.1 External Interrupts .............................................................................................. 55 3.4.2 Internal Interrupts ............................................................................................... 57 3.4.3 Interrupt Handling Sequence .............................................................................. 57 3.4.4 Interrupt Response Time..................................................................................... 59 Usage Notes ........................................................................................................................ 61 3.5.1 Interrupts after Reset........................................................................................... 61 3.5.2 Notes on Stack Area Use .................................................................................... 61 3.5.3 Notes on Rewriting Port Mode Registers ........................................................... 61
Section 4 Address Break ..................................................................................... 63
4.1 Register Descriptions.......................................................................................................... 64 4.1.1 Address Break Control Register (ABRKCR) ..................................................... 64 4.1.2 Address Break Status Register (ABRKSR) ........................................................ 66 4.1.3 Break Address Registers E, H, L (BARE, BARH, BARL) ................................ 66 4.1.4 Break Data Registers H, L (BDRH, BDRL)....................................................... 66 Operation ............................................................................................................................ 67
4.2
Section 5 Clock Pulse Generators ....................................................................... 69
5.1 System Clock Generator ..................................................................................................... 70 5.1.1 Connecting Crystal Resonator ............................................................................ 70 5.1.2 Connecting Ceramic Resonator .......................................................................... 71 5.1.3 External Clock Input Method.............................................................................. 71 Subclock Generator ............................................................................................................ 72 5.2.1 Connecting 32.768-kHz Crystal Resonator ........................................................ 72 5.2.2 Pin Connection when not Using Subclock.......................................................... 73 Prescalers ............................................................................................................................ 73 5.3.1 Prescaler S .......................................................................................................... 73 5.3.2 Prescaler W......................................................................................................... 73 Usage Notes ........................................................................................................................ 74 5.4.1 Notes on Resonators ........................................................................................... 74 5.4.2 Notes on Board Design ....................................................................................... 74
5.2
5.3
5.4
Rev. 3.00 Mar. 15, 2006 Page x of xxxii
Section 6 Power-Down Modes ............................................................................75
6.1 Register Descriptions.......................................................................................................... 75 6.1.1 System Control Register 1 (SYSCR1) ................................................................ 76 6.1.2 System Control Register 2 (SYSCR2) ................................................................ 77 6.1.3 Module Standby Control Register 1 (MSTCR1) ................................................ 79 6.1.4 Module Standby Control Register 2 (MSTCR2) ................................................ 80 Mode Transitions and States of LSI.................................................................................... 81 6.2.1 Sleep Mode ......................................................................................................... 84 6.2.2 Standby Mode ..................................................................................................... 84 6.2.3 Subsleep Mode.................................................................................................... 85 6.2.4 Subactive Mode .................................................................................................. 85 Operating Frequency in Active Mode................................................................................. 86 Direct Transition ................................................................................................................. 86 6.4.1 Direct Transition from Active Mode to Subactive Mode.................................... 86 6.4.2 Direct Transition from Subactive Mode to Active Mode.................................... 87 Module Standby Function................................................................................................... 87
6.2
6.3 6.4
6.5
Section 7 ROM ....................................................................................................89
7.1 7.2 Block Configuration ........................................................................................................... 90 Register Descriptions.......................................................................................................... 91 7.2.1 Flash Memory Control Register 1 (FLMCR1).................................................... 91 7.2.2 Flash Memory Control Register 2 (FLMCR2).................................................... 92 7.2.3 Erase Block Register 1 (EBR1) .......................................................................... 93 7.2.4 Flash Memory Power Control Register (FLPWCR) ........................................... 94 7.2.5 Flash Memory Enable Register (FENR) ............................................................. 94 On-Board Programming Modes.......................................................................................... 95 7.3.1 Boot Mode .......................................................................................................... 95 7.3.2 Programming/Erasing in User Program Mode.................................................... 98 Flash Memory Programming/Erasing............................................................................... 100 7.4.1 Program/Program-Verify .................................................................................. 100 7.4.2 Erase/Erase-Verify............................................................................................ 103 7.4.3 Interrupt Handling when Programming/Erasing Flash Memory....................... 103 Program/Erase Protection ................................................................................................. 105 7.5.1 Hardware Protection ......................................................................................... 105 7.5.2 Software Protection........................................................................................... 105 7.5.3 Error Protection................................................................................................. 105 Programmer Mode ............................................................................................................ 106 Power-Down States for Flash Memory............................................................................. 106
7.3
7.4
7.5
7.6 7.7
Rev. 3.00 Mar. 15, 2006 Page xi of xxxii
Section 8 RAM .................................................................................................. 109 Section 9 I/O Ports............................................................................................. 111
9.1 Port 1................................................................................................................................. 111 9.1.1 Port Mode Register 1 (PMR1) .......................................................................... 112 9.1.2 Port Control Register 1 (PCR1) ........................................................................ 113 9.1.3 Port Data Register 1 (PDR1) ............................................................................ 113 9.1.4 Port Pull-Up Control Register 1 (PUCR1)........................................................ 114 9.1.5 Pin Functions .................................................................................................... 114 Port 2................................................................................................................................. 116 9.2.1 Port Control Register 2 (PCR2) ........................................................................ 117 9.2.2 Port Data Register 2 (PDR2) ............................................................................ 117 9.2.3 Port Mode Register 3 (PMR3) .......................................................................... 118 9.2.4 Pin Functions .................................................................................................... 118 Port 3................................................................................................................................. 120 9.3.1 Port Control Register 3 (PCR3) ........................................................................ 120 9.3.2 Port Data Register 3 (PDR3) ............................................................................ 121 9.3.3 Pin Functions .................................................................................................... 121 Port 5................................................................................................................................. 123 9.4.1 Port Mode Register 5 (PMR5) .......................................................................... 124 9.4.2 Port Control Register 5 (PCR5) ........................................................................ 125 9.4.3 Port Data Register 5 (PDR5) ............................................................................ 125 9.4.4 Port Pull-Up Control Register 5 (PUCR5)........................................................ 126 9.4.5 Pin Functions .................................................................................................... 126 Port 6................................................................................................................................. 129 9.5.1 Port Control Register 6 (PCR6) ........................................................................ 129 9.5.2 Port Data Register 6 (PDR6) ............................................................................ 130 9.5.3 Pin Functions .................................................................................................... 130 Port 7................................................................................................................................. 134 9.6.1 Port Control Register 7 (PCR7) ........................................................................ 134 9.6.2 Port Data Register 7 (PDR7) ............................................................................ 135 9.6.3 Pin Functions .................................................................................................... 135 Port 8................................................................................................................................. 137 9.7.1 Port Control Register 8 (PCR8) ........................................................................ 138 9.7.2 Port Data Register 8 (PDR8) ............................................................................ 138 9.7.3 Pin Functions .................................................................................................... 139 Port 9................................................................................................................................. 141 9.8.1 Port Control Register 9 (PCR9) ........................................................................ 142 9.8.2 Port Data Register 9 (PDR9) ............................................................................ 142 9.8.3 Pin Functions .................................................................................................... 143
9.2
9.3
9.4
9.5
9.6
9.7
9.8
Rev. 3.00 Mar. 15, 2006 Page xii of xxxii
9.9
Port B ................................................................................................................................ 145 9.9.1 Port Data Register B (PDRB) ........................................................................... 145
Section 10 Realtime Clock (RTC) .....................................................................147
10.1 10.2 10.3 Features............................................................................................................................. 147 Input/Output Pin ............................................................................................................... 148 Register Descriptions........................................................................................................ 148 10.3.1 Second Data Register/Free Running Counter Data Register (RSECDR) ......... 149 10.3.2 Minute Data Register (RMINDR)..................................................................... 150 10.3.3 Hour Data Register (RHRDR) .......................................................................... 151 10.3.4 Day-of-Week Data Register (RWKDR) ........................................................... 152 10.3.5 RTC Control Register 1 (RTCCR1).................................................................. 153 10.3.6 RTC Control Register 2 (RTCCR2).................................................................. 155 10.3.7 Clock Source Select Register (RTCCSR) ......................................................... 156 Operation .......................................................................................................................... 157 10.4.1 Initial Settings of Registers after Power-On ..................................................... 157 10.4.2 Initial Setting Procedure ................................................................................... 157 10.4.3 Data Reading Procedure ................................................................................... 158 Interrupt Sources............................................................................................................... 159
10.4
10.5
Section 11 Timer B1 ..........................................................................................161
11.1 11.2 11.3 Features............................................................................................................................. 161 Input/Output Pin ............................................................................................................... 161 Register Descriptions........................................................................................................ 162 11.3.1 Timer Mode Register B1 (TMB1) .................................................................... 162 11.3.2 Timer Counter B1 (TCB1)................................................................................ 163 11.3.3 Timer Load Register B1 (TLB1) ...................................................................... 163 Operation .......................................................................................................................... 163 11.4.1 Interval Timer Operation .................................................................................. 163 11.4.2 Auto-Reload Timer Operation .......................................................................... 164 11.4.3 Event Counter Operation .................................................................................. 164 Timer B1 Operating Modes .............................................................................................. 164
11.4
11.5
Section 12 Timer V............................................................................................165
12.1 12.2 12.3 Features............................................................................................................................. 165 Input/Output Pins.............................................................................................................. 167 Register Descriptions........................................................................................................ 167 12.3.1 Timer Counter V (TCNTV) .............................................................................. 167 12.3.2 Time Constant Registers A, B (TCORA, TCORB) .......................................... 168 12.3.3 Timer Control Register V0 (TCRV0) ............................................................... 169
Rev. 3.00 Mar. 15, 2006 Page xiii of xxxii
12.4 12.5
12.6
12.3.4 Timer Control/Status Register V (TCSRV) ...................................................... 170 12.3.5 Timer Control Register V1 (TCRV1) ............................................................... 172 Operation .......................................................................................................................... 173 12.4.1 Timer V Operation............................................................................................ 173 Timer V Application Examples ........................................................................................ 176 12.5.1 Pulse Output with Arbitrary Duty Cycle........................................................... 176 12.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input .......... 177 Usage Notes ...................................................................................................................... 178
Section 13 Timer W........................................................................................... 181
13.1 13.2 13.3 Features............................................................................................................................. 181 Input/Output Pins.............................................................................................................. 184 Register Descriptions........................................................................................................ 184 13.3.1 Timer Mode Register W (TMRW) ................................................................... 185 13.3.2 Timer Control Register W (TCRW) ................................................................. 186 13.3.3 Timer Interrupt Enable Register W (TIERW) .................................................. 187 13.3.4 Timer Status Register W (TSRW) .................................................................... 188 13.3.5 Timer I/O Control Register 0 (TIOR0) ............................................................. 189 13.3.6 Timer I/O Control Register 1 (TIOR1) ............................................................. 191 13.3.7 Timer Counter (TCNT)..................................................................................... 192 13.3.8 General Registers A to D (GRA to GRD)......................................................... 193 Operation .......................................................................................................................... 194 13.4.1 Normal Operation ............................................................................................. 194 13.4.2 PWM Operation................................................................................................ 199 Operation Timing.............................................................................................................. 204 13.5.1 TCNT Count Timing ........................................................................................ 204 13.5.2 Output Compare Timing................................................................................... 205 13.5.3 Input Capture Timing........................................................................................ 206 13.5.4 Timing of Counter Clearing by Compare Match .............................................. 206 13.5.5 Buffer Operation Timing .................................................................................. 207 13.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match ............................. 208 13.5.7 Timing of IMFA to IMFD Setting at Input Capture ......................................... 209 13.5.8 Timing of Status Flag Clearing......................................................................... 209 Usage Notes ...................................................................................................................... 210
13.4
13.5
13.6
Section 14 Timer Z............................................................................................ 213
14.1 14.2 14.3 Features............................................................................................................................. 213 Input/Output Pins.............................................................................................................. 218 Register Descriptions........................................................................................................ 219 14.3.1 Timer Start Register (TSTR) ............................................................................ 220
Rev. 3.00 Mar. 15, 2006 Page xiv of xxxii
14.4
14.5
14.6
14.3.2 Timer Mode Register (TMDR) ......................................................................... 221 14.3.3 Timer PWM Mode Register (TPMR) ............................................................... 222 14.3.4 Timer Function Control Register (TFCR)......................................................... 223 14.3.5 Timer Output Master Enable Register (TOER) ................................................ 225 14.3.6 Timer Output Control Register (TOCR) ........................................................... 227 14.3.7 Timer Counter (TCNT)..................................................................................... 228 14.3.8 General Registers A, B, C, and D (GRA, GRB, GRC, and GRD).................... 228 14.3.9 Timer Control Register (TCR).......................................................................... 229 14.3.10 Timer I/O Control Register (TIORA and TIORC)............................................ 230 14.3.11 Timer Status Register (TSR)............................................................................. 232 14.3.12 Timer Interrupt Enable Register (TIER) ........................................................... 234 14.3.13 PWM Mode Output Level Control Register (POCR) ....................................... 235 14.3.14 Interface with CPU ........................................................................................... 236 Operation .......................................................................................................................... 237 14.4.1 Counter Operation............................................................................................. 237 14.4.2 Waveform Output by Compare Match.............................................................. 241 14.4.3 Input Capture Function ..................................................................................... 244 14.4.4 Synchronous Operation..................................................................................... 247 14.4.5 PWM Mode ...................................................................................................... 248 14.4.6 Reset Synchronous PWM Mode ....................................................................... 254 14.4.7 Complementary PWM Mode............................................................................ 258 14.4.8 Buffer Operation ............................................................................................... 268 14.4.9 Timer Z Output Timing .................................................................................... 276 Interrupts........................................................................................................................... 278 14.5.1 Status Flag Set Timing...................................................................................... 278 14.5.2 Status Flag Clearing Timing ............................................................................. 280 Usage Notes ...................................................................................................................... 281
Section 15 Watchdog Timer ..............................................................................289
15.1 15.2 Features............................................................................................................................. 289 Register Descriptions........................................................................................................ 290 15.2.1 Timer Control/Status Register WD (TCSRWD)............................................... 290 15.2.2 Timer Counter WD (TCWD)............................................................................ 292 15.2.3 Timer Mode Register WD (TMWD) ................................................................ 292 Operation .......................................................................................................................... 293
15.3
Section 16 14-Bit PWM.....................................................................................295
16.1 16.2 16.3 Features............................................................................................................................. 295 Input/Output Pin ............................................................................................................... 295 Register Descriptions........................................................................................................ 296
Rev. 3.00 Mar. 15, 2006 Page xv of xxxii
16.4
16.3.1 PWM Control Register (PWCR) ...................................................................... 296 16.3.2 PWM Data Registers U, L (PWDRU, PWDRL) .............................................. 297 Operation .......................................................................................................................... 297
Section 17 Serial Communication Interface 3 (SCI3)....................................... 299
17.1 17.2 17.3 Features............................................................................................................................. 299 Input/Output Pins.............................................................................................................. 303 Register Descriptions........................................................................................................ 303 17.3.1 Receive Shift Register (RSR) ........................................................................... 303 17.3.2 Receive Data Register (RDR)........................................................................... 303 17.3.3 Transmit Shift Register (TSR) .......................................................................... 304 17.3.4 Transmit Data Register (TDR).......................................................................... 304 17.3.5 Serial Mode Register (SMR) ............................................................................ 304 17.3.6 Serial Control Register 3 (SCR3) ..................................................................... 306 17.3.7 Serial Status Register (SSR) ............................................................................. 307 17.3.8 Bit Rate Register (BRR) ................................................................................... 309 Operation in Asynchronous Mode .................................................................................... 318 17.4.1 Clock................................................................................................................. 318 17.4.2 SCI3 Initialization............................................................................................. 319 17.4.3 Data Transmission ............................................................................................ 320 17.4.4 Serial Data Reception ....................................................................................... 322 Operation in Clocked Synchronous Mode ........................................................................ 326 17.5.1 Clock................................................................................................................. 326 17.5.2 SCI3 Initialization............................................................................................. 326 17.5.3 Serial Data Transmission .................................................................................. 327 17.5.4 Serial Data Reception (Clocked Synchronous Mode) ...................................... 329 17.5.5 Simultaneous Serial Data Transmission and Reception.................................... 331 Multiprocessor Communication Function ........................................................................ 332 17.6.1 Multiprocessor Serial Data Transmission ......................................................... 334 17.6.2 Multiprocessor Serial Data Reception .............................................................. 335 Interrupt Requests............................................................................................................. 338 Usage Notes ...................................................................................................................... 339 17.8.1 Break Detection and Processing ....................................................................... 339 17.8.2 Mark State and Break Sending ......................................................................... 339 17.8.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only).................................................................. 339 17.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ................................................................................................................. 340
17.4
17.5
17.6
17.7 17.8
Rev. 3.00 Mar. 15, 2006 Page xvi of xxxii
Section 18 I2C Bus Interface 2 (IIC2) ................................................................341
18.1 18.2 18.3 Features............................................................................................................................. 341 Input/Output Pins.............................................................................................................. 343 Register Descriptions........................................................................................................ 344 18.3.1 I2C Bus Control Register 1 (ICCR1)................................................................. 344 18.3.2 I2C Bus Control Register 2 (ICCR2)................................................................. 347 18.3.3 I2C Bus Mode Register (ICMR)........................................................................ 348 18.3.4 I2C Bus Interrupt Enable Register (ICIER) ....................................................... 350 18.3.5 I2C Bus Status Register (ICSR)......................................................................... 352 18.3.6 Slave Address Register (SAR).......................................................................... 355 18.3.7 I2C Bus Transmit Data Register (ICDRT)......................................................... 356 18.3.8 I2C Bus Receive Data Register (ICDRR).......................................................... 356 18.3.9 I2C Bus Shift Register (ICDRS)........................................................................ 356 Operation .......................................................................................................................... 357 18.4.1 I2C Bus Format.................................................................................................. 357 18.4.2 Master Transmit Operation ............................................................................... 358 18.4.3 Master Receive Operation................................................................................. 360 18.4.4 Slave Transmit Operation ................................................................................. 362 18.4.5 Slave Receive Operation................................................................................... 364 18.4.6 Clocked Synchronous Serial Format................................................................. 366 18.4.7 Noise Canceller................................................................................................. 368 18.4.8 Example of Use................................................................................................. 369 Interrupts........................................................................................................................... 373 Bit Synchronous Circuit.................................................................................................... 374 Usage Notes ...................................................................................................................... 375 18.7.1 Issue (Retransmission) of Start/Stop Conditions .............................................. 375 18.7.2 WAIT Setting in I2C Bus Mode Register (ICMR) ............................................ 375
18.4
18.5 18.6 18.7
Section 19 A/D Converter..................................................................................377
19.1 19.2 19.3 Features............................................................................................................................. 377 Input/Output Pins.............................................................................................................. 379 Register Descriptions........................................................................................................ 380 19.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .......................................... 380 19.3.2 A/D Control/Status Register (ADCSR) ............................................................ 381 19.3.3 A/D Control Register (ADCR) ......................................................................... 382 Operation .......................................................................................................................... 384 19.4.1 Single Mode...................................................................................................... 384 19.4.2 Scan Mode ........................................................................................................ 384 19.4.3 Input Sampling and A/D Conversion Time ...................................................... 385
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19.4
19.5 19.6
19.4.4 External Trigger Input Timing.......................................................................... 386 A/D Conversion Accuracy Definitions ............................................................................. 387 Usage Notes ...................................................................................................................... 390 19.6.1 Permissible Signal Source Impedance .............................................................. 390 19.6.2 Influences on Absolute Accuracy ..................................................................... 390
Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional) ........................................................................................ 391
20.1 20.2 Features............................................................................................................................. 391 Register Descriptions........................................................................................................ 393 20.2.1 Low-Voltage-Detection Control Register (LVDCR)........................................ 393 20.2.2 Low-Voltage-Detection Status Register (LVDSR)........................................... 395 Operation .......................................................................................................................... 396 20.3.1 Power-On Reset Circuit .................................................................................... 396 20.3.2 Low-Voltage Detection Circuit......................................................................... 397
20.3
Section 21 Power Supply Circuit ...................................................................... 401
21.1 21.2 When Using Internal Power Supply Step-Down Circuit .................................................. 401 When Not Using Internal Power Supply Step-Down Circuit ........................................... 402
Section 22 List of Registers............................................................................... 403
22.1 22.2 22.3 Register Addresses (Address Order)................................................................................. 404 Register Bits ..................................................................................................................... 411 Register States in Each Operating Mode .......................................................................... 417
Section 23 Electrical Characteristics ................................................................. 423
23.1 23.2 Absolute Maximum Ratings ............................................................................................. 423 Electrical Characteristics (F-ZTATTM Version)................................................................. 423 23.2.1 Power Supply Voltage and Operating Ranges .................................................. 423 23.2.2 DC Characteristics ............................................................................................ 426 23.2.3 AC Characteristics ............................................................................................ 433 23.2.4 A/D Converter Characteristics.......................................................................... 437 23.2.5 Watchdog Timer Characteristics....................................................................... 438 23.2.6 Flash Memory Characteristics .......................................................................... 439 23.2.7 Power-Supply-Voltage Detection Circuit Characteristics (Optional) ............... 441 23.2.8 Power-On Reset Circuit Characteristics (Optional).......................................... 442 Electrical Characteristics (Masked ROM Version)........................................................... 442 23.3.1 Power Supply Voltage and Operating Ranges .................................................. 442 23.3.2 DC Characteristics ............................................................................................ 445 23.3.3 AC Characteristics ............................................................................................ 452
23.3
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23.4 23.5
23.3.4 A/D Converter Characteristics .......................................................................... 456 23.3.5 Watchdog Timer Characteristics....................................................................... 457 23.3.6 Power-Supply-Voltage Detection Circuit Characteristics (Optional) ............... 458 23.3.7 Power-On Reset Circuit Characteristics (Optional) .......................................... 459 Operation Timing.............................................................................................................. 459 Output Load Condition ..................................................................................................... 461
Appendix..............................................................................................................463
A. Instruction Set ................................................................................................................... 463 A.1 Instruction List...................................................................................................... 463 A.2 Operation Code Map............................................................................................. 478 A.3 Number of Execution States ................................................................................. 481 A.4 Combinations of Instructions and Addressing Modes .......................................... 492 I/O Ports............................................................................................................................ 493 B.1 I/O Port Block Diagrams ...................................................................................... 493 B.2 Port States in Each Operating Mode ..................................................................... 511 Product Code Lineup ........................................................................................................ 512 Package Dimensions ......................................................................................................... 513
B.
C. D.
Main Revisions and Additions in this Edition .....................................................515 Index ....................................................................................................................521
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Figures
Section 1 Overview Figure 1.1 Internal Block Diagram ................................................................................................. 3 Figure 1.2 Pin Arrangements (FP-80A).......................................................................................... 4 Section 2 CPU Figure 2.1 Memory Map............................................................................................................... 10 Figure 2.2 CPU Registers ............................................................................................................. 11 Figure 2.3 Usage of General Registers ......................................................................................... 12 Figure 2.4 Relationship between Stack Pointer and Stack Area ................................................... 13 Figure 2.5 General Register Data Formats (1).............................................................................. 15 Figure 2.5 General Register Data Formats (2).............................................................................. 16 Figure 2.6 Memory Data Formats................................................................................................. 17 Figure 2.7 Instruction Formats...................................................................................................... 27 Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 30 Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 33 Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 34 Figure 2.11 CPU Operation States................................................................................................ 35 Figure 2.12 State Transitions ........................................................................................................ 36 Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same Address...................................................................................................................... 37 Section 3 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Section 4 Figure 4.1 Figure 4.2 Figure 4.2 Section 5 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.6 Exception Handling Reset Sequence............................................................................................................ 56 Stack Status after Exception Handling ........................................................................ 58 Interrupt Sequence....................................................................................................... 60 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 62 Address Break Block Diagram of Address Break................................................................................ 63 Address Break Interrupt Operation Example (1)......................................................... 67 Address Break Interrupt Operation Example (2)......................................................... 68 Clock Pulse Generators Block Diagram of Clock Pulse Generators.................................................................. 69 Block Diagram of System Clock Generator ................................................................ 70 Typical Connection to Crystal Resonator.................................................................... 70 Equivalent Circuit of Crystal Resonator...................................................................... 70 Typical Connection to Ceramic Resonator.................................................................. 71 Example of External Clock Input ................................................................................ 71
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Figure 5.7 Block Diagram of Subclock Generator ....................................................................... 72 Figure 5.8 Typical Connection to 32.768-kHz Crystal Resonator................................................ 72 Figure 5.9 Equivalent Circuit of 32.768-kHz Crystal Resonator.................................................. 72 Figure 5.10 Pin Connection when not Using Subclock ................................................................ 73 Figure 5.11 Example of Incorrect Board Design ........................................................................... 74 Section 6 Power-Down Modes Figure 6.1 Mode Transition Diagram ........................................................................................... 81 Section 7 Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 Section 9 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Figure 9.6 Figure 9.7 Figure 9.8 Figure 9.9 ROM Block Configuration of Flash Memory ....................................................................... 90 Programming/Erasing Flowchart Example in User Program Mode............................ 99 Program/Program-Verify Flowchart ......................................................................... 101 Erase/Erase-Verify Flowchart ................................................................................... 104 I/O Ports Port 1 Pin Configuration............................................................................................ 111 Port 2 Pin Configuration............................................................................................ 116 Port 3 Pin Configuration............................................................................................ 120 Port 5 Pin Configuration............................................................................................ 123 Port 6 Pin Configuration............................................................................................ 129 Port 7 Pin Configuration............................................................................................ 134 Port 8 Pin Configuration............................................................................................ 137 Port 9 Pin Configuration............................................................................................ 141 Port B Pin Configuration........................................................................................... 145 Realtime Clock (RTC) Block Diagram of RTC ........................................................................................... 147 Definition of Time Expression ................................................................................ 154 Initial Setting Procedure.......................................................................................... 157 Example: Reading of Inaccurate Time Data............................................................ 158
Section 10 Figure 10.1 Figure 10.2 Figure 10.3 Figure 10.4
Section 11 Timer B1 Figure 11.1 Block Diagram of Timer B1.................................................................................... 161 Section 12 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Figure 12.6 Figure 12.7 Timer V Block Diagram of Timer V ..................................................................................... 166 Increment Timing with Internal Clock .................................................................... 174 Increment Timing with External Clock................................................................... 174 OVF Set Timing ...................................................................................................... 174 CMFA and CMFB Set Timing................................................................................ 175 TMOV Output Timing ............................................................................................ 175 Clear Timing by Compare Match............................................................................ 175
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Figure 12.8 Clear Timing by TMRIV Input ............................................................................... 176 Figure 12.9 Pulse Output Example ............................................................................................. 176 Figure 12.10 Example of Pulse Output Synchronized to TRGV Input....................................... 177 Figure 12.11 Contention between TCNTV Write and Clear ...................................................... 178 Figure 12.12 Contention between TCORA Write and Compare Match ..................................... 179 Figure 12.13 Internal Clock Switching and TCNTV Operation ................................................. 179 Section 13 Timer W Figure 13.1 Block Diagram of Timer W..................................................................................... 183 Figure 13.2 Free-Running Counter Operation ............................................................................ 194 Figure 13.3 Periodic Counter Operation..................................................................................... 195 Figure 13.4 0 and 1 Output Example (TOA = 0, TOB = 1)........................................................ 195 Figure 13.5 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 196 Figure 13.6 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 196 Figure 13.7 Input Capture Operating Example........................................................................... 197 Figure 13.8 Buffer Operation Example (Input Capture)............................................................. 198 Figure 13.9 PWM Mode Example (1) ........................................................................................ 199 Figure 13.10 PWM Mode Example (2) ...................................................................................... 200 Figure 13.11 Buffer Operation Example (Output Compare) ...................................................... 201 Figure 13.12 PWM Mode Example (TOB = 0, TOC = 0, TOD = 0: Initial Output Values are Set to 0) ....................... 202 Figure 13.13 PWM Mode Example (TOB = 1, TOC = 1,and TOD = 1: Initial Output Values are Set to 1) ................. 203 Figure 13.14 Count Timing for Internal Clock Source ............................................................... 204 Figure 13.15 Count Timing for External Clock Source.............................................................. 204 Figure 13.16 Output Compare Output Timing ........................................................................... 205 Figure 13.17 Input Capture Input Signal Timing........................................................................ 206 Figure 13.18 Timing of Counter Clearing by Compare Match................................................... 206 Figure 13.19 Buffer Operation Timing (Compare Match).......................................................... 207 Figure 13.20 Buffer Operation Timing (Input Capture) ............................................................. 207 Figure 13.21 Timing of IMFA to IMFD Flag Setting at Compare Match .................................. 208 Figure 13.22 Timing of IMFA to IMFD Flag Setting at Input Capture...................................... 209 Figure 13.23 Timing of Status Flag Clearing by CPU................................................................ 209 Figure 13.24 Contention between TCNT Write and Clear ......................................................... 210 Figure 13.25 Internal Clock Switching and TCNT Operation.................................................... 211 Figure 13.26 When Compare Match and Bit Manipulation Instruction to TCRW Occur at the Same Timing ......................................................................................................... 212 Section 14 Timer Z Figure 14.1 Timer Z Block Diagram .......................................................................................... 215 Figure 14.2 Timer Z (Channel 0) Block Diagram ...................................................................... 216
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Figure 14.3 Timer Z (Channel 1) Block Diagram ...................................................................... 217 Figure 14.4 Example of Outputs in Reset Synchronous PWM Mode and Complementary PWM Mode............................................................................................................. 224 Figure 14.5 Accessing Operation of 16-Bit Register (between CPU and TCNT (16 bits))........ 236 Figure 14.6 Accessing Operation of 8-Bit Register (between CPU and TSTR (8 bits)) ............ 236 Figure 14.7 Example of Counter Operation Setting Procedure .................................................. 237 Figure 14.8 Free-Running Counter Operation ............................................................................ 238 Figure 14.9 Periodic Counter Operation..................................................................................... 239 Figure 14.10 Count Timing at Internal Clock Operation............................................................ 239 Figure 14.11 Count Timing at External Clock Operation (Both Edges Detected)...................... 240 Figure 14.12 Example of Setting Procedure for Waveform Output by Compare Match............ 241 Figure 14.13 Example of 0 Output/1 Output Operation ............................................................. 242 Figure 14.14 Example of Toggle Output Operation ................................................................... 243 Figure 14.15 Output Compare Timing ....................................................................................... 243 Figure 14.16 Example of Input Capture Operation Setting Procedure ....................................... 244 Figure 14.17 Example of Input Capture Operation .................................................................... 245 Figure 14.18 Input Capture Signal Timing................................................................................. 246 Figure 14.19 Example of Synchronous Operation Setting Procedure ........................................ 247 Figure 14.20 Example of Synchronous Operation...................................................................... 248 Figure 14.21 Example of PWM Mode Setting Procedure .......................................................... 249 Figure 14.22 Example of PWM Mode Operation (1) ................................................................. 250 Figure 14.23 Example of PWM Mode Operation (2) ................................................................. 251 Figure 14.24 Example of PWM Mode Operation (3) ................................................................. 252 Figure 14.25 Example of PWM Mode Operation (4) ................................................................. 253 Figure 14.26 Example of Reset Synchronous PWM Mode Setting Procedure........................... 255 Figure 14.27 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 1) ...... 256 Figure 14.28 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0) ...... 257 Figure 14.29 Example of Complementary PWM Mode Setting Procedure................................ 259 Figure 14.30 Canceling Procedure of Complementary PWM Mode.......................................... 260 Figure 14.31 Example of Complementary PWM Mode Operation (1) ...................................... 261 Figure 14.32 (1) Example of Complementary PWM Mode Operation (TPSC2 = TPSC1 = TPSC0 = 0) (2)................................................................ 263 Figure 14.32 (2) Example of Complementary PWM Mode Operation (TPSC2 = TPSC1 = TPSC0 0) (3)................................................................ 264 Figure 14.33 Timing of Overshooting ........................................................................................ 265 Figure 14.34 Timing of Undershooting ...................................................................................... 265 Figure 14.35 Compare Match Buffer Operation......................................................................... 268 Figure 14.36 Input Capture Buffer Operation............................................................................. 269 Figure 14.37 Example of Buffer Operation Setting Procedure................................................... 269
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Figure 14.38 Example of Buffer Operation (1) (Buffer Operation for Output Compare Register).................................................. 270 Figure 14.39 Example of Compare Match Timing for Buffer Operation ................................... 271 Figure 14.40 Example of Buffer Operation (2) (Buffer Operation for Input Capture Register) ...................................................... 272 Figure 14.41 Input Capture Timing of Buffer Operation............................................................ 273 Figure 14.42 Buffer Operation (3) (Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1) ............ 274 Figure 14.43 Buffer Operation (4) (Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1) ............ 275 Figure 14.44 Example of Output Disable Timing of Timer Z by Writing to TOER .................. 276 Figure 14.45 Example of Output Disable Timing of Timer Z by External Trigger.................... 277 Figure 14.46 Example of Output Inverse Timing of Timer Z by Writing to TFCR ................... 277 Figure 14.47 Example of Output Inverse Timing of Timer Z by Writing to POCR................... 278 Figure 14.48 IMF Flag Set Timing when Compare Match Occurs ............................................ 279 Figure 14.49 IMF Flag Set Timing at Input Capture .................................................................. 279 Figure 14.50 OVF Flag Set Timing ............................................................................................ 280 Figure 14.51 Status Flag Clearing Timing.................................................................................. 280 Figure 14.52 Contention between TCNT Write and Clear Operations....................................... 281 Figure 14.53 Contention between TCNT Write and Increment Operations ............................... 281 Figure 14.54 Contention between GR Write and Compare Match ............................................. 282 Figure 14.55 Contention between TCNT Write and Overflow................................................... 283 Figure 14.56 Contention between GR Read and Input Capture.................................................. 284 Figure 14.57 Contention between Count Clearing and Increment Operations by Input Capture .................................................................................................................. 285 Figure 14.58 Contention between GR Write and Input Capture................................................. 286 Figure 14.59 When Compare Match and Bit Manipulation Instruction to TOCR Occur at the Same Timing ......................................................................................................... 287 Section 15 Watchdog Timer Figure 15.1 Block Diagram of Watchdog Timer ........................................................................ 289 Figure 15.2 Watchdog Timer Operation Example...................................................................... 293 Section 16 14-Bit PWM Figure 16.1 Block Diagram of 14-Bit PWM .............................................................................. 295 Figure 16.2 Waveform Output by 14-Bit PWM ......................................................................... 298 Section 17 Figure 17.1 Figure 17.2 Figure 17.3 Serial Communication Interface 3 (SCI3) Block Diagram of SCI3 ........................................................................................... 302 Data Format in Asynchronous Communication ...................................................... 318 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) ............. 318
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Figure 17.4 Sample SCI3 Initialization Flowchart ..................................................................... 319 Figure 17.5 Example of SCI3 Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) ........................................................................... 320 Figure 17.6 Sample Serial Transmission Data Flowchart (Asynchronous Mode)...................... 321 Figure 17.7 Example of SCI3 Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) ........................................................................... 322 Figure 17.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (1) ..................... 324 Figure 17.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (2) ..................... 325 Figure 17.9 Data Format in Clocked Synchronous Communication .......................................... 326 Figure 17.10 Example of SCI3 Transmission in Clocked Synchronous Mode .......................... 327 Figure 17.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode) ................ 328 Figure 17.12 Example of SCI3 Reception in Clocked Synchronous Mode................................ 329 Figure 17.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)...................... 330 Figure 17.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations (Clocked Synchronous Mode)............................................................................... 331 Figure 17.15 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) .......................................... 333 Figure 17.16 Sample Multiprocessor Serial Transmission Flowchart ........................................ 334 Figure 17.17 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 335 Figure 17.17 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 336 Figure 17.18 Example of SCI3 Reception Using Multiprocessor Format (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 337 Figure 17.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 340 Section 18 I2C Bus Interface 2 (IIC2) Figure 18.1 Block Diagram of I2C Bus Interface 2..................................................................... 342 Figure 18.2 External Circuit Connections of I/O Pins ................................................................ 343 Figure 18.3 I2C Bus Formats ...................................................................................................... 357 Figure 18.4 I2C Bus Timing........................................................................................................ 357 Figure 18.5 Master Transmit Mode Operation Timing (1)......................................................... 359 Figure 18.6 Master Transmit Mode Operation Timing (2)......................................................... 359 Figure 18.7 Master Receive Mode Operation Timing (1) .......................................................... 361 Figure 18.8 Master Receive Mode Operation Timing (2) .......................................................... 362 Figure 18.9 Slave Transmit Mode Operation Timing (1) ........................................................... 363 Figure 18.10 Slave Transmit Mode Operation Timing (2) ......................................................... 364 Figure 18.11 Slave Receive Mode Operation Timing (1)........................................................... 365 Figure 18.12 Slave Receive Mode Operation Timing (2)........................................................... 365 Figure 18.13 Clocked Synchronous Serial Transfer Format....................................................... 366 Figure 18.14 Transmit Mode Operation Timing......................................................................... 367 Figure 18.15 Receive Mode Operation Timing .......................................................................... 368 Figure 18.16 Block Diagram of Noise Canceller........................................................................ 368
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Figure 18.17 Figure 18.18 Figure 18.19 Figure 18.20 Figure 18.21 Section 19 Figure 19.1 Figure 19.2 Figure 19.3 Figure 19.4 Figure 19.4 Figure 19.5
Sample Flowchart for Master Transmit Mode....................................................... 369 Sample Flowchart for Master Receive Mode ........................................................ 370 Sample Flowchart for Slave Transmit Mode......................................................... 371 Sample Flowchart for Slave Receive Mode .......................................................... 372 Timing of Bit Synchronous Circuit ....................................................................... 374
A/D Converter Block Diagram of A/D Converter ........................................................................... 378 A/D Conversion Timing .......................................................................................... 385 External Trigger Input Timing ................................................................................ 386 A/D Conversion Accuracy Definitions (1) .............................................................. 388 A/D Conversion Accuracy Definitions (2) .............................................................. 389 Analog Input Circuit Example................................................................................. 390
Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional) Figure 20.1 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit...................................................................................................................... 392 Figure 20.2 Operational Timing of Power-On Reset Circuit...................................................... 396 Figure 20.3 Operational Timing of LVDR Circuit ..................................................................... 398 Figure 20.4 Operational Timing of LVDI Circuit....................................................................... 399 Figure 20.5 Timing for Operation/Release of Low-Voltage Detection Circuit .......................... 400 Section 21 Power Supply Circuit Figure 21.1 Power Supply Connection when Internal Step-Down Circuit is Used .................... 401 Figure 21.2 Power Supply Connection when Internal Step-Down Circuit is Not Used ............. 402 Section 23 Figure 23.1 Figure 23.2 Figure 23.3 Figure 23.4 Figure 23.5 Figure 23.6 Figure 23.7 Appendix Figure B.1 Figure B.2 Figure B.3 Figure B.4 Figure B.5 Figure B.6 Figure B.7 Electrical Characteristics System Clock Input Timing..................................................................................... 459 RES Low Width Timing.......................................................................................... 459 Input Timing............................................................................................................ 460 I2C Bus Interface Input/Output Timing ................................................................... 460 SCK3 Input Clock Timing....................................................................................... 460 SCI Input/Output Timing in Clocked Synchronous Mode ...................................... 461 Output Load Circuit................................................................................................. 461 Port 1 Block Diagram (P17) ..................................................................................... 493 Port 1 Block Diagram (P14, P16) ............................................................................. 494 Port 1 Block Diagram (P15) ..................................................................................... 495 Port 1 Block Diagram (P12) ..................................................................................... 495 Port 1 Block Diagram (P11) ..................................................................................... 496 Port 1 Block Diagram (P10) ..................................................................................... 497 Port 2 Block Diagram (P24, P23) ............................................................................. 497
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Figure B.8 Port 2 Block Diagram (P22) ..................................................................................... 498 Figure B.9 Port 2 Block Diagram (P21) ..................................................................................... 498 Figure B.10 Port 2 Block Diagram (P20) ................................................................................... 499 Figure B.11 Port 3 Block Diagram (P37 to P30) ........................................................................ 499 Figure B.12 Port 5 Block Diagram (P57, P56) ........................................................................... 500 Figure B.13 Port 5 Block Diagram (P55) ................................................................................... 501 Figure B.14 Port 5 Block Diagram (P54 to P50) ........................................................................ 502 Figure B.15 Port 6 Block Diagram (P67 to P60) ........................................................................ 503 Figure B.16 Port 7 Block Diagram (P77) ................................................................................... 503 Figure B.17 Port 7 Block Diagram (P76) ................................................................................... 504 Figure B.18 Port 7 Block Diagram (P75) ................................................................................... 504 Figure B.19 Port 7 Block Diagram (P74) ................................................................................... 505 Figure B.20 Port 7 Block Diagram (P72) ................................................................................... 506 Figure B.21 Port 7 Block Diagram (P71) ................................................................................... 506 Figure B.22 Port 7 Block Diagram (P70) ................................................................................... 507 Figure B.23 Port 8 Block Diagram (P87 to P85) ........................................................................ 507 Figure B.24 Port 8 Block Diagram (P84 to P81) ........................................................................ 508 Figure B.25 Port8 Block Diagram (P80) .................................................................................... 508 Figure B.26 Port 9 Block Diagram (P97 to P93) ........................................................................ 509 Figure B.27 Port 9 Block Diagram (P92) ................................................................................... 509 Figure B.28 Port 9 Block Diagram (P91) ................................................................................... 510 Figure B.29 Port 9 Block Diagram (P90) ................................................................................... 510 Figure B.30 Port B Block Diagram (PB7 to PB0) ...................................................................... 511 Figure D.1 FP-80A Package Dimensions ................................................................................... 513
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Tables
Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 5 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 18 Table 2.2 Data Transfer Instructions....................................................................................... 19 Table 2.3 Arithmetic Operations Instructions (1) ................................................................... 20 Table 2.3 Arithmetic Operations Instructions (2) ................................................................... 21 Table 2.4 Logic Operations Instructions................................................................................. 22 Table 2.5 Shift Instructions..................................................................................................... 22 Table 2.6 Bit Manipulation Instructions (1)............................................................................ 23 Table 2.6 Bit Manipulation Instructions (2)............................................................................ 24 Table 2.7 Branch Instructions ................................................................................................. 25 Table 2.8 System Control Instructions.................................................................................... 26 Table 2.9 Block Data Transfer Instructions ............................................................................ 26 Table 2.10 Addressing Modes .................................................................................................. 28 Table 2.11 Absolute Address Access Ranges ........................................................................... 29 Table 2.12 Effective Address Calculation (1)........................................................................... 31 Table 2.12 Effective Address Calculation (2)........................................................................... 32 Section 3 Exception Handling Table 3.1 Exception Sources and Vector Address .................................................................. 44 Table 3.2 Interrupt Wait States ............................................................................................... 59 Section 4 Address Break Table 4.1 Access and Data Bus Used ..................................................................................... 65 Section 5 Clock Pulse Generators Table 5.1 Crystal Resonator Parameters ................................................................................. 71 Section 6 Power-Down Modes Table 6.1 Operating Frequency and Waiting Time................................................................. 77 Table 6.2 Transition Mode after SLEEP Instruction Execution and Transition Mode due to Interrupt .................................................................................................................. 82 Table 6.3 Internal State in Each Operating Mode................................................................... 83 Section 7 ROM Table 7.1 Setting Programming Modes .................................................................................. 95 Table 7.2 Boot Mode Operation ............................................................................................. 97
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Table 7.3 Table 7.4 Table 7.5 Table 7.6 Table 7.7
System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible................................................................................................................... 98 Reprogram Data Computation Table .................................................................... 102 Additional-Program Data Computation Table ...................................................... 102 Programming Time ............................................................................................... 102 Flash Memory Operating States............................................................................ 107
Section 10 Realtime Clock (RTC) Table 10.1 Pin Configuration.................................................................................................. 148 Table 10.2 Interrupt Sources................................................................................................... 159 Section 11 Timer B1 Table 11.1 Pin Configuration.................................................................................................. 161 Table 11.2 Timer B1 Operating Modes .................................................................................. 164 Section 12 Timer V Table 12.1 Pin Configuration.................................................................................................. 167 Table 12.2 Clock Signals to Input to TCNTV and Counting Conditions ............................... 170 Section 13 Timer W Table 13.1 Timer W Functions ............................................................................................... 182 Table 13.2 Pin Configuration.................................................................................................. 184 Section 14 Timer Z Table 14.1 Timer Z Functions ................................................................................................ 214 Table 14.2 Pin Configuration.................................................................................................. 218 Table 14.3 Initial Output Level of FTIOB0 Pin...................................................................... 249 Table 14.4 Output Pins in Reset Synchronous PWM Mode................................................... 254 Table 14.5 Register Settings in Reset Synchronous PWM Mode........................................... 254 Table 14.6 Output Pins in Complementary PWM Mode........................................................ 258 Table 14.7 Register Settings in Complementary PWM Mode................................................ 258 Table 14.8 Register Combinations in Buffer Operation ......................................................... 268 Section 16 14-Bit PWM Table 16.1 Pin Configuration.................................................................................................. 295 Section 17 Serial Communication Interface 3 (SCI3) Table 17.1 Channel Configuration.......................................................................................... 300 Table 17.2 Pin Configuration.................................................................................................. 303 Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 310 Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 312 Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ...... 314 Table 17.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 315
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Table 17.5 Table 17.5 Table 17.6 Table 17.7
Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1).......................................................................................................................... 316 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2).......................................................................................................................... 317
SSR Status Flags and Receive Data Handling ...................................................... 323 SCI3 Interrupt Requests........................................................................................ 338
Section 18 I2C Bus Interface 2 (IIC2) Table 18.1 Pin Configuration.................................................................................................. 343 Table 18.2 Transfer Rate ........................................................................................................ 346 Table 18.3 Interrupt Requests ................................................................................................. 373 Table 18.4 Time for Monitoring SCL..................................................................................... 374 Section 19 A/D Converter Table 19.1 Pin Configuration.................................................................................................. 379 Table 19.2 Analog Input Channels and Corresponding ADDR Registers .............................. 380 Table 19.3 A/D Conversion Time (Single Mode)................................................................... 386 Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional) Table 20.1 LVDCR Settings and Select Functions................................................................. 394 Section 23 Electrical Characteristic Table 23.1 Absolute Maximum Ratings ................................................................................. 423 Table 23.2 DC Characteristics (1)........................................................................................... 426 Table 23.2 DC Characteristics (2)........................................................................................... 432 Table 23.3 AC Characteristics ................................................................................................ 433 Table 23.4 I2C Bus Interface Timing ...................................................................................... 435 Table 23.5 Serial Communication Interface (SCI) Timing..................................................... 436 Table 23.6 A/D Converter Characteristics .............................................................................. 437 Table 23.7 Watchdog Timer Characteristics........................................................................... 438 Table 23.8 Flash Memory Characteristics .............................................................................. 439 Table 23.9 Power-Supply-Voltage Detection Circuit Characteristics..................................... 441 Table 23.10 Power-On Reset Circuit Characteristics............................................................ 442 Table 23.11 DC Characteristics (1)....................................................................................... 445 Table 23.11 DC Characteristics (2)....................................................................................... 451 Table 23.12 AC Characteristics ............................................................................................ 452 Table 23.13 I2C Bus Interface Timing .................................................................................. 454 Table 23.14 Serial Communication Interface (SCI) Timing................................................. 455 Table 23.15 A/D Converter Characteristics .......................................................................... 456 Table 23.16 Watchdog Timer Characteristics....................................................................... 457 Table 23.17 Power-Supply-Voltage Detection Circuit Characteristics................................. 458 Table 23.18 Power-On Reset Circuit Characteristics............................................................ 459
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Appendix Table A.1 Table A.2 Table A.2 Table A.2 Table A.3 Table A.4 Table A.5
Instruction Set....................................................................................................... 465 Operation Code Map (1) ....................................................................................... 478 Operation Code Map (2) ....................................................................................... 479 Operation Code Map (3) ....................................................................................... 480 Number of Cycles in Each Instruction.................................................................. 482 Number of Cycles in Each Instruction.................................................................. 483 Combinations of Instructions and Addressing Modes .......................................... 492
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Section 1 Overview
Section 1 Overview
1.1 Features
* High-speed H8/300H central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 CPU on an object level Sixteen 16-bit general registers 62 basic instructions * Various peripheral functions RTC (can be used as a free running counter) Timer B1 (8-bit timer) Timer V (8-bit timer) Timer W (16-bit timer) Timer Z (16-bit timer) 14-bit PWM Watchdog timer SCI3 (Asynchronous or clocked synchronous serial communication interface) x 3 channels I2C bus interface 2 (conforms to the I2C bus interface format that is advocated by Philips Electronics) 10-bit A/D converter POR/LVD (Power-on reset and low voltage detection circuit) * On-chip memory
Model
On-Chip PowerOn Reset and Low-Voltage
Product Classification
Flash memory version (F-ZTAT
TM
Standard Version
H8/36049F HD64F36049
Detecting Circuit Version
ROM
RAM
4 kbytes
HD64F36049G 96 kbytes
version) H8/36049 H8/36048 H8/36047
TM
Masked ROM version
HD64336049 HD64336048 HD64336047
HD64336049G 96 kbytes HD64336048G 80 kbytes HD64336047G 64 kbytes
3 kbytes 3 kbytes 3 kbytes
Note: F-ZTAT is a trademark of Renesas Technology Corp.
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Section 1 Overview
* General I/O ports I/O pins: 59 I/O pins, including 13 large current ports (IOL = 20 mA, @VOL = 1.5 V) Input-only pins: 8 input pins (also used for analog input) * Supports various power-down modes * Compact package
Package QFP-80 Code FP-80A Body Size 14.0 x 14.0 mm Pin Pitch 0.65 mm
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Section 1 Overview
1.2
Internal Block Diagram
OSC1 OSC2 TEST RES VCL NMI VCC VSS VSS
Subclock generator
X1 X2
System clock generator
CPU H8/300H
P17/IRQ3/TRGV P16/IRQ2 P15/IRQ1/TMIB1 P14/IRQ0 P12 P11/PWM P10/TMOW P24 P23 P22/TXD P21/RXD P20/SCK3 P37 P36 P35 P34 P33 P32 P31 P31
Data bus (lower) P67/FTIOD1 P66/FTIOC1 P65/FTIOB1 P64/FTIOA1 P63/FTIOD0 P62/FTIOC0 P61/FTIOB0 P60/FTIOA0 P77 P76/TMOV P75/TMCIV P74/TMRIV P72/TXD_2 P71/RXD_2 P70/SCK3_2 P87 P86 P85 P84/FTIOD P83/FTIOC P82/FTIOB P81/FTIOA P80/FTCI
ROM IIC2
RTC
SCI3
14-bit PWM
SCI3_2
Timer Z
SCI3_3
P57/SCL P56/SDA P55/WKP5/ADTRG P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0
Timer V
Watchdog timer
Timer W
Timer B1
Port 8
A/D converter POR and LVD (option) Data bus (upper) Address bus Port B
Port 7 AVCC AVSS
Port 6 Port 9
Figure 1.1 Internal Block Diagram
PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0
Port 1 Port 2 Port 3 Port 5
RAM
P97 P96 P95 P94 P93 P92/TXD_3 P91/RXD_3 P90/SCK3_3
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Section 1 Overview
1.3
Pin Arrangement
P90/SCK3_3 P67/FTIOD1 P66/FTIOC1 P63/FTIOD0 P62/FTIOC0 P65/FTIOB1 P64/FTIOA1 P61/FTIOB0 P60/FTIOA0 P91/RXD_3 P10/TMOW P84/FTIOD P83/FTIOC P82/FTIOB P81/FTIOA P20/SCK3
P11/PWM
P80/FTCI
P12
P92/TXD_3 P93 P94 P95 P96 P97 P70/SCK3_2 P71/RXD_2 P72/TXD_2 P74/TMRIV P75/TMCIV P76/TMOV P77 AVss PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 H8/36049 Group Top view 31 30 29 28 27 26 25 24 23 22 1
PB6/AN6
Vss
P21/RXD P22/TXD P23 P24 P50/WKP0 P51/WKP1 P52/WKP2 P53/WKP3 P54/WKP4 P55/WKP5/ADTRG P56/SDA P57/SCL P17/IRQ3/TRGV P16/IRQ2 P15/IRQ1/TMIB1 P14/IRQ0 P30 P31 P32 P33
2
PB7/AN7
3
AVcc
4
X2
5
X1
6
VCL
7
RES
8
TEST
21 9 10 11 12 13 14 15 16 17 18 19 20
OSC2 OSC1 NMI Vss Vcc P87 P86 P85 P37 P36 P35 P34
Figure 1.2 Pin Arrangements (FP-80A)
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Section 1 Overview
1.4
Table 1.1
Pin Functions
Pin Functions
Pin No.
Type Power supply pins
Symbol Vcc Vss AVcc
FP-80A 12 9, 50 3
I/O Input Input Input
Functions Power supply pin. Connect this pin to the system power supply. Ground pin. Ensure to connect all pins to the system power supply (0 V). Analog power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply. Analog ground pin for the A/D converter. Connect this pin to the system power supply (0 V). Internal step-down power supply pin. Connect a capacitor of around 0.1 F between this pin and the Vss pin for stabilization. These pins connect with crystal or ceramic resonator for the system clock, or can be used to input an external clock. See section 5, Clock Pulse Generators, for a typical connection. These pins connect with a 32.768 kHz crystal resonator for the subclock. See section 5, Clock Pulse Generators, for a typical connection. Reset pin. The pull-up resistor (typ.150 k) is incorporated. When driven low, the chip is reset. Test pin. Connect this pin to Vss. Non-maskable interrupt request input pin. Be sure to pull-up by a pull-up resistor. External interrupt request input pins. Can select the rising or falling edge. External interrupt request input pins. Can select the rising or falling edge. This is an output pin for divided clocks. External event input pin.
AVss
74
Input
VCL
6
Input
Clock pins
OSC1 OSC2
11 10
Input Output
X1 X2 System control RES TEST External interrupt pins NMI IRQ0 to IRQ3 WKP0 to WKP5 RTC Timer B1 TMOW TMIB1
5 4 7 8 13 25 to 28 36 to 31 56 26
Input Output Input Input Input Input Input Output Input
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Section 1 Overview
Pin No. Type Timer V Symbol TMOV TMCIV TMRIV TRGV Timer Z FTIOA0 FTIOB0 FTIOC0 FP-80A 72 71 70 28 42 43 44 I/O Functions
Output This is an output pin for waveforms generated by the output compare function. Input Input Input I/O I/O I/O External event input pin. Counter reset input pin. Count start trigger input pin. Output compare output/input capture input/external clock input pin Output compare output/input capture input/PWM output pin Output compare output/input capture input/PWM synchronous output pin (at a reset or in complementary PWM mode) Output compare output/input capture input/PWM output pin Output compare output/input capture input/PWM output pin (at a reset or in complementary PWM mode) Output compare output/input capture input/PWM output pin External event input pin Output compare output/input capture input/PWM output pin
FTIOD0 FTIOA1
45 46
I/O I/O
FTIOB1 to FTIOD1 Timer W FTCI FTIOA to FTIOD 14-bit PWM PWM I C bus interface 2 (IIC2)
2
47 to 49 51 52 to 55 57 30
I/O Input I/O
Output 14-bit PWM square wave output pin I/O IIC data I/O pin. Can directly drive a bus by NMOS open-drain output. When using this pin, external pull-up resistor is required. IIC clock I/O pin. Can directly drive a bus by NMOS open-drain output. When using this pin, external pull-up resistor is required.
SDA
SCL
29
I/O
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Section 1 Overview
Pin No. Type Serial communication interface 3 (SCI3) Symbol TXD TXD_2 TXD_3 RXD RXD_2 RXD_3 SCK3 SCK3_2 SCK3_3 A/D converter FP-80A 39 69 61 40 68 60 41 67 59 I/O Functions
Output Transmit data output pin
Input
Receive data input pin
I/O
Clock I/O pin
AN7 to AN0 2, 1, 80 to 75 ADTRG 31
Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O
Analog input pin Conversion start trigger input pin 8-bit input port 7-bit I/O port 5-bit I/O port 8-bit I/O port 8-bit I/O port 8-bit I/O port 7-bit I/O port 8-bit I/O port 8-bit I/O port
I/O ports
PB7 to PB0 2, 1, 80 to 75 P17 to P14, 28 to 25, P12 to P10 58 to 56 P24 to P20 P37 to P30 P57 to P50 P67 to P60 37 to 41 17 to 24 29 to 36 49 to 42
P77 to P74, 73 to 70, P72 to P70 69 to 67 P87 to P80 P97 to P90 14 to 16, 55 to 51 66 to 59
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Section 1 Overview
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Section 2 CPU
Section 2 CPU
This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300CPU, and supports only advanced mode, which has a 16-Mbyte address space. * Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs Additional eight 16-bit extended registers 32-bit transfer and arithmetic and logic instructions are added Signed multiply and divide instructions are added. * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers and eight 16-bit registers, or eight 32-bit registers * 62 basic instructions 8/16/32-bit data transfer and arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space * High-speed operation All frequently-used instructions execute in two to four states 8/16/32-bit register-register add/subtract : 2 state 8 x 8-bit register-register multiply : 14 states 16 / 8-bit register-register divide : 14 states 16 x 16-bit register-register multiply : 22 states 32 / 16-bit register-register divide : 22 states
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Section 2 CPU
* Power-down state Transition to power-down state by SLEEP instruction
2.1
Address Space and Memory Map
The address space of this LSI is 16 Mbytes, which includes the program area and data area. Figure 2.1 shows the memory map.
HD64F36049 HD64F36049G (Flash memory version) H'000000 H'00008B H'00008C Interrupt vector H'000000 H'00008B H'00008C HD64336049 HD64336049G (Masked ROM version) Interrupt vector H'000000 H'00008B H'00008C HD64336048 HD64336048G (Masked ROM version) Interrupt vector H'000000 H'00008B H'00008C HD64336047 HD64336047G (Masked ROM version) Interrupt vector
On-chip ROM (64 kbytes) On-chip ROM (80 kbytes) On-chip ROM (96 kbytes) On-chip ROM (96 kbytes) H'00FFFF
H'013FFF Not used H'017FFF Not used H'FFE800 On-chip RAM (2 kbytes) H'FFEFFF Not used H'FFF600 H'FFF77F H'FFF780 H'FFFB7F H'FFFB80 H'FFFF7F H'FFFF80 Internal I/O register H'FFFFFF H'FFFFFF Internal I/O register (1-kbyte work area for flash memory programming) On-chip RAM (2 kbytes) (1-kbyte user area) H'FFFB80 H'FFFF7F H'FFFF80 Internal I/O register H'FFFFFF H'FFF600 H'FFF77F H'FFEFFF Not used Internal I/O register Not used H'FFFB80 H'FFFF7F H'FFFF80 Internal I/O register H'FFFFFF H'FFF600 H'FFF77F H'FFE800 On-chip RAM (2 kbytes) H'FFEFFF Not used Internal I/O register Not used H'FFFB80 H'FFFF7F H'FFFF80 Internal I/O register H'FFF600 H'FFF77F H'017FFF Not used H'FFE800 On-chip RAM (2 kbytes) H'FFEFFF Not used Internal I/O register Not used H'FFE800 On-chip RAM (2 kbytes) Not used
On-chip RAM (1 kbyte)
On-chip RAM (1 kbyte)
On-chip RAM (1 kbyte)
Figure 2.1 Memory Map
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Section 2 CPU
2.2
Register Configuration
The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition-code register (CCR).
General Registers (ERn)
15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 E0 E1 E2 E3 E4 E5 E6 E7 (SP) 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0
Control Registers (CR)
23 PC 0
76543210
[Legend]
SP: PC: CCR: I: UI: Stack pointer Program counter Condition-code register Interrupt mask bit User bit H: U: N: Z: V: C: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag
CCR I UI H U N Z V C
Figure 2.2 CPU Registers
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Section 2 CPU
2.2.1
General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-bit registers. The usage of each register can be selected independently.
* Address registers * 32-bit registers * 16-bit registers * 8-bit registers
E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) RH registers (R0H to R7H)
Figure 2.3 Usage of General Registers General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the relationship between the stack pointer and the stack area.
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Section 2 CPU
Empty area SP (ER7)
Stack area
Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0). The PC is initialized when the start address is loaded by the vector address generated during reset exception-handling sequence. 2.2.3 Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1 by reset exception-handling sequence, but other bits are not initialized. Some instructions leave flag bits unchanged. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. For the action of each instruction on the flag bits, see appendix A.1, Instruction List.
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Section 2 CPU
Bit 7
Initial Bit Name Value I 1
R/W R/W
Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence.
6
UI
Undefined R/W
User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions.
5
H
Undefined R/W
Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise.
4
U
Undefined R/W
User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions.
3
N
Undefined R/W
Negative Flag Stores the value of the most significant bit of data as a sign bit.
2
Z
Undefined R/W
Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
1
V
Undefined R/W
Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times.
0
C
Undefined R/W
Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit manipulation instructions.
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Section 2 CPU
2.3
Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.3.1 General Register Data Formats
Figure 2.5 shows the data formats in general registers.
Data Type General Register RnH 1-bit data Data Format 7 0 Don't care 7 1-bit data RnL Don't care 0 76 54 32 10
76 54 32 10
7 4-bit BCD data RnH Upper
43 Lower
0 Don't care
7 4-bit BCD data RnL Don't care Upper
43 Lower
0
7 Byte data RnH MSB
0 Don't care LSB 7 0 LSB
Byte data
RnL
Don't care MSB
Figure 2.5 General Register Data Formats (1)
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Section 2 CPU
Data Type
General Register Rn
Data Format
Word data
15 MSB 15 MSB Longword data ERn 31 16 15 0 LSB
0 LSB
Word data
En
0
MSB
LSB
[Legend] ERn: General register ER En: Rn: General register E General register R
RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit
Figure 2.5 General Register Data Formats (2)
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Section 2 CPU
2.3.2
Memory Data Formats
Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches. When ER7 (SP) is used as an address register to access the stack area, the operand size should be word or longword.
Data Type Address
7 1-bit data Address L 7 6 5 4 3 2 1
Data Format
0 0
Byte data
Address L
MSB
LSB
Word data
Address 2M Address 2M+1
MSB LSB
Longword data
Address 2N Address 2N+1 Address 2N+2 Address 2N+3
MSB
LSB
Figure 2.6 Memory Data Formats
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Section 2 CPU
2.4
2.4.1
Instruction Set
List of Instructions Classified by Function
The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below. Table 2.1
Symbol Rd Rs Rn ERn (EAd) (EAs) CCR N Z V C PC SP #IMM disp + - x / ~
Operation Notation
Description General register (destination)* General register (source)* General register* General register (32-bit register or address register) Destination operand Source operand Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical XOR Move NOT (logical complement)
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Section 2 CPU
Symbol :3/:8/:16/:24 Note: *
Description 3-, 8-, 16-, or 24-bit length
General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7).
Table 2.2
Instruction MOV
Data Transfer Instructions
Size* B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) Rd Cannot be used in this LSI. Rs (EAs) Cannot be used in this LSI. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP.
MOVFPE MOVTPE POP
B B W/L
PUSH
W/L
Note:
* Refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.3
Instruction ADD SUB
Arithmetic Operations Instructions (1)
Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd (decimal adjust) Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder.
ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU
B
B/W/L
L B
B/W
MULXS
B/W
DIVXU
B/W
Note:
* Refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.3
Instruction DIVXS
Arithmetic Operations Instructions (2)
Size* B/W Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit.
CMP
B/W/L
NEG
B/W/L
EXTU
W/L
EXTS
W/L
Note:
* Refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.4
Instruction AND
Logic Operations Instructions
Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. ~ (Rd) (Rd) Takes the one's complement (logical complement) of general register contents.
OR
B/W/L
XOR
B/W/L
NOT
B/W/L
Note:
* Refers to the operand size. B: Byte W: Word L: Longword
Table 2.5
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note:
Shift Instructions
Size* B/W/L B/W/L B/W/L B/W/L Function Rd (shift) Rd Performs an arithmetic shift on general register contents. Rd (shift) Rd Performs a logical shift on general register contents. Rd (rotate) Rd Rotates general register contents. Rd (rotate) Rd Rotates general register contents through the carry flag.
* Refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.6
Instruction BSET
Bit Manipulation Instructions (1)
Size* B Function 1 ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. 0 ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ~ ( of ) ( of ) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ~ ( of ) Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. C ( of ) C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ~ ( of ) C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ( of ) C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ~ ( of ) C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
BCLR
B
BNOT
B
BTST
B
BAND
B
BIAND
B
BOR
B
BIOR
B
Note:
* Refers to the operand size. B: Byte
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Section 2 CPU
Table 2.6
Instruction BXOR
Bit Manipulation Instructions (2)
Size* B Function C ( of ) C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ~ ( of ) C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. ( of ) C Transfers a specified bit in a general register or memory operand to the carry flag. ~ ( of ) C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. C ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand. ~ C ( of ) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data.
BIXOR
B
BLD
B
BILD
B
BST
B
BIST
B
Note:
* Refers to the operand size. B: Byte
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Section 2 CPU
Table 2.7
Instruction Bcc*
Branch Instructions
Size -- Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z(N V) = 0 Z(N V) = 1
JMP BSR JSR RTS Note: *
-- -- -- --
Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine
Bcc is the general name for conditional branch instructions.
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Section 2 CPU
Table 2.8
Instruction TRAPA RTE SLEEP LDC
System Control Instructions
Size* Function -- -- -- B/W Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access. CCR (EAd) Transfers the CCR contents to a destination location. The condition code register size is one byte, but in transfer to memory, data is written by word access. CCR #IMM CCR Logically ANDs the CCR with immediate data. CCR #IMM CCR Logically ORs the CCR with immediate data. CCR #IMM CCR Logically XORs the CCR with immediate data. PC + 2 PC Only increments the program counter.
STC
B/W
ANDC ORC XORC NOP Note:
B B B --
* Refers to the operand size. B: Byte W: Word
Table 2.9
Instruction EEPMOV.B
Block Data Transfer Instructions
Size -- Function if R4L 0 then Repeat @ER5+ @ER6+, R4L-1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5+ @ER6+, R4-1 R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed.
EEPMOV.W --
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Section 2 CPU
2.4.2
Basic Instruction Formats
H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.7 shows examples of instruction formats. * Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register Field Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. * Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A 24-bit address or displacement is treated as a 32-bit data in which the upper 8 bits are 0 (H'00). * Condition Field Specifies the branching condition of Bcc instructions.
(1) Operation field only op NOP, RTS, etc.
(2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension op EA(disp) rn rm MOV.B @(d:16, Rn), Rm
(4) Operation field, effective address extension, and condition field op cc EA(disp) BRA d:8
Figure 2.7 Instruction Formats
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Section 2 CPU
2.5
2.5.1
Addressing Modes and Effective Address Calculation
Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses a subset of these addressing modes. Addressing modes that can be used differ depending on the instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing Modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit-manipulation instructions use register direct, register indirect, or the absolute addressing mode (@aa:8) to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.10 Addressing Modes
No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:24,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
Register Direct--Rn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. Register Indirect--@ERn The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory.
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Register Indirect with Displacement--@(d:16, ERn) or @(d:24, ERn) A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand. A 16-bit displacement is sign-extended when added. Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn * Register indirect with post-increment--@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. For the word or longword access, the register value should be even. * Register indirect with pre-decrement--@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the lower 24 bits of the result is the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For the word or longword access, the register value should be even. Absolute Address--@aa:8, @aa:16, @aa:24 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24) For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the entire address space. The access ranges of absolute addresses for the group of this LSI are those shown in table 2.11. Table 2.11 Absolute Address Access Ranges
Absolute Address 8 bits (@aa:8) 16 bits (@aa:16) 24 bits (@aa:24) Access Range H'FFFF00 to H'FFFFFF H'000000 to H'007FFF H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF
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Immediate--#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. Program-Counter Relative--@(d:8, PC) or @(d:16, PC) This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. Memory Indirect--@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The memory operand is accessed by longword access. The first byte of the memory operand is ignored, generating a 24-bit branch address. Figure 2.8 shows how to specify branch address for in memory indirect mode. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF). Note that the first part of the address range is also the exception vector area.
Specified by @aa:8
Dummy Branch address
Figure 2.8 Branch Address Specification in Memory Indirect Mode
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Section 2 CPU
2.5.2
Effective Address Calculation
Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI, a 24-bit effective address is generated. Table 2.12 Effective Address Calculation (1)
No 1
Addressing Mode and Instruction Format
Register direct(Rn)
Effective Address Calculation
Effective Address (EA)
Operand is general register contents.
op 2
rm
rn 31
General register contents
Register indirect(@ERn)
0
23
0
op 3
r
Register indirect with displacement @(d:16,ERn) or @(d:24,ERn)
31
General register contents
0 23 0
op
r
disp 31
Sign extension
0 disp
4
Register indirect with post-increment or pre-decrement *Register indirect with post-increment @ERn+
31
General register contents
0
23
0
op
r 31
1, 2, or 4
*Register indirect with pre-decrement @-ERn
0
General register contents
23
0
op
r
1, 2, or 4
The value to be added or subtracted is 1 when the operand is byte size, 2 for word size, and 4 for longword size.
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Section 2 CPU
Table 2.12 Effective Address Calculation (2)
No 5
Addressing Mode and Instruction Format Absolute address Effective Address Calculation Effective Address (EA)
@aa:8 op abs
23 H'FFFF
87
0
@aa:16 op abs
23
16 15
0
Sign extension
@aa:24 op abs 23 0
6
Immediate
#xx:8/#xx:16/#xx:32 op IMM
Operand is immediate data.
7
Program-counter relative @(d:8,PC) @(d:16,PC) op disp
23
PC contents
0
23
Sign extension
0 disp 23 0
8
Memory indirect @@aa:8
op
abs
23 H'0000 15
87 abs
0
0
Memory contents
23 16 15 H'00
0
[Legend] r, rm,rn : Register field : Operation field op : Displacement disp : Immediate data IMM : Absolute address abs
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Section 2 CPU
2.6
Basic Bus Cycle
CPU operation is synchronized by a system clock () or a subclock (SUB). The period from a rising edge of or SUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
Bus cycle T1 state or SUB T2 state
Internal address bus
Address
Internal read signal Internal data bus (read access)
Read data
Internal write signal Internal data bus (write access)
Write data
Figure 2.9 On-Chip Memory Access Cycle
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Section 2 CPU
2.6.2
On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For details on the data bus width and number of accessing states of each register, refer to section 22, List of Registers. Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data bus width can be accessed by byte or word size. When a register with 8-bit data bus width is accessed by word size, access is completed in two cycles. In two-state access, the operation timing is the same as that for on-chip memory. Figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral module.
Bus cycle T1 state or SUB T2 state T3 state
Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access)
Address
Read data
Write data
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
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Section 2 CPU
2.7
CPU States
There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode and subactive mode. For the program halt state, there are a sleep mode, standby mode, and sub-sleep mode. These states are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and program halt state, refer to section 6, Power-Down Modes. For details on exception processing, refer to section 3, Exception Handling.
CPU state
Reset state The CPU is initialized Program execution state
Active (high speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock Subactive mode The CPU executes successive program instructions at reduced speed, synchronized by the subclock
Power-down modes
Program halt state A state in which some or all of the chip functions are stopped to conserve power
Sleep mode
Standby mode
Subsleep mode Exceptionhandling state A transient state in which the CPU changes the processing flow due to a reset or an interrupt
Figure 2.11 CPU Operation States
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Section 2 CPU
Reset cleared Reset state Reset occurs Exception-handling state
Reset occurs
Reset occurs
Interrupt source
Interrupt source
Exceptionhandling complete
Program halt state SLEEP instruction executed
Program execution state
Figure 2.12 State Transitions
2.8
2.8.1
Usage Notes
Notes on Data Access to Empty Areas
The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user. When data is transferred from CPU to empty areas, the transferred data will be lost. This action may also cause the CPU to malfunction. When data is transferred from an empty area to CPU, the contents of the data cannot be guaranteed. 2.8.2 EEPMOV Instruction
EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4 or R4L, which starts from the address indicated by ER5, to the address indicated by ER6. Set R4 or R4L and ER6 so that the end address of the destination address (value of ER6 + R4 or ER6 + R4L) does not exceed H'FFFFFF (the value of ER6 must not change from H'FFFFFF to H'000000 during execution).
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Section 2 CPU
2.8.3
Bit Manipulation Instruction
The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units. Special care is required when using these instructions in cases where two registers are assigned to the same address, or when a bit is directly manipulated for a port or a register containing a write-only bit, because this may rewrite data of a bit other than the bit to be manipulated. Bit manipulation for two registers assigned to the same address Example 1: Bit manipulation for the timer load register and timer counter (Applicable for timer B1 in the H8/36049 Group.) Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address. When a bit-manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations takes place. 1. Data is read in byte units. 2. The CPU sets or resets the bit to be manipulated with the bit-manipulation instruction. 3. The written data is written again in byte units to the timer load register. The timer is counting, so the value read is not necessarily the same as the value in the timer load register. As a result, bits other than the intended bit in the timer counter may be modified and the modified value may be written to the timer load register.
Read Count clock Timer counter
Reload Write Timer load register
Internal data bus
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same Address
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Section 2 CPU
Example 2: The BSET instruction is executed for port 5. P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level signal at P50 with a BSET instruction is shown below. * Prior to executing BSET instruction
P57 Input/output Pin state PCR5 PDR5 Input Low level 0 1 P56 Input High level 0 0 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Output Low level 1 0
* BSET instruction executed instruction BSET #0, @PDR5 The BSET instruction is executed for port 5.
* After executing BSET instruction
P57 Input/output Pin state PCR5 PDR5 Input Low level 0 0 P56 Input High level 0 1 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Output High level 1 1
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Section 2 CPU
* Description on operation 1. When the BSET instruction is executed, first the CPU reads port 5. Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level input). P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a value of H'80, but the value read by the CPU is H'40. 2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41. 3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET instruction. As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR5. * Prior to executing BSET instruction MOV.B MOV.B MOV.B #80, R0L, R0L,
P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 1
R0L @RAM0 @PDR5
P56 Input High level 0 0 0
The PDR5 value (H'80) is written to a work area in memory (RAM0) as well as to PDR5.
P55 Output Low level 1 0 0
P54 Output Low level 1 0 0
P53 Output Low level 1 0 0
P52 Output Low level 1 0 0
P51 Output Low level 1 0 0
P50 Output Low level 1 0 0
* BSET instruction executed BSET #0, @RAM0 The BSET instruction is executed designating the PDR5 work area (RAM0).
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Section 2 CPU
* After executing BSET instruction MOV.B MOV.B @RAM0, R0L R0L, @PDR5
P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 1 P56 Input High level 0 0 0
The work area (RAM0) value is written to PDR5.
P55 Output Low level 1 0 0
P54 Output Low level 1 0 0
P53 Output Low level 1 0 0
P52 Output Low level 1 0 0
P51 Output Low level 1 0 0
P50 Output High level 1 1 1
Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be input to this input pin. * Prior to executing BCLR instruction
P57 Input/output Pin state PCR5 PDR5 Input Low level 0 1 P56 Input High level 0 0 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Output Low level 1 0
* BCLR instruction executed BCLR #0, @PCR5 The BCLR instruction is executed for PCR5.
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Section 2 CPU
* After executing BCLR instruction
P57 Input/output Pin state PCR5 PDR5 Output Low level 1 1 P56 Output High level 1 0 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Input High level 0 0
* Description on operation 1. When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only register, the CPU reads a value of H'FF, even though the PCR5 value is actually H'3F. 2. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. 3. Finally, H'FE is written to PCR5 and BCLR instruction execution ends. As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However, bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins. To prevent this problem, store a copy of the PCR5 data in a work area in memory and manipulate data of the bit in the work area, then write this data to PCR5. * Prior to executing BCLR instruction MOV.B MOV.B MOV.B #3F, R0L, R0L,
P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 0
R0L @RAM0 @PCR5
P56 Input High level 0 0 0
The PCR5 value (H'3F) is written to a work area in memory (RAM0) as well as to PCR5.
P55 Output Low level 1 0 1
P54 Output Low level 1 0 1
P53 Output Low level 1 0 1
P52 Output Low level 1 0 1
P51 Output Low level 1 0 1
P50 Output Low level 1 0 1
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Section 2 CPU
* BCLR instruction executed BCLR #0, @RAM0 The BCLR instructions executed for the PCR5 work area (RAM0).
* After executing BCLR instruction MOV.B MOV.B @RAM0, R0L R0L, @PCR5
P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 0 P56 Input High level 0 0 0
The work area (RAM0) value is written to PCR5.
P55 Output Low level 1 0 1
P54 Output Low level 1 0 1
P53 Output Low level 1 0 1
P52 Output Low level 1 0 1
P51 Output Low level 1 0 1
P50 Output High level 0 0 0
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Section 3 Exception Handling
Section 3 Exception Handling
Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. * Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling starts. Exception handling is the same as exception handling by the RES pin. * Trap Instruction Exception handling starts when a trap instruction (TRAPA) is executed. The TRAPA instruction generates a vector address corresponding to a vector number from 0 to 3, as specified in the instruction code. Exception handling can be executed at all times in the program execution state, regardless of the setting of the I bit in CCR. * Interrupts External interrupts other than NMI and internal interrupts other than address break are masked by the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when the current instruction or exception handling ends, if an interrupt request has been issued.
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Section 3 Exception Handling
3.1
Exception Sources and Vector Address
Table 3.1 shows the vector addresses and priority of each exception handling. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority. Table 3.1 Exception Sources and Vector Address
Exception Sources Reset Reserved for system use NMI Trap instruction #0 Trap instruction #1 Trap instruction #2 Trap instruction #3 Address break CPU External interrupt pin Break conditions satisfied Direct transition by executing the SLEEP instruction IRQ0 Low-voltage detection interrupt* IRQ1 IRQ2 IRQ3 WKP Vector Number 0 1 to 6 7 8 9 10 11 12 13 14 15 16 17 18 Vector Address H'000000 to H'000003 H'000004 to H'00001B H'00001C to H'00001F H'000020 to H'000023 H'000024 to H'000027 H'000028 to H'00002B H'00002C to H'00002F H'000030 to H'000033 H'000034 to H'000037 H'000038 to H'00003B H'00003C to H'00003F H'000040 to H'000043 H'000044 to H'000047 H'000048 to H'00004B Low Priority High
Relative Module RES pin Watchdog timer External interrupt pin CPU
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Section 3 Exception Handling
Relative Module RTC Timer W
Exception Sources Overflow Reserved for system use
Vector Number 19 20
Vector Address H'00004C to H'00004F H'000050 to H'000053 H'000054 to H'000057
Priority High
Input capture A/compare match A 21 Input capture B/compare match B Input capture C/compare match C Input capture D/compare match D Overflow Compare match A Compare match B Overflow Receive data full Transmit data empty Transmit end Receive error Transmit data empty Transmit end Receive data full Arbitration lost/overrun error NACK detection Stop conditions detected A/D conversion end 22
Timer V
H'000058 to H'00005B H'00005C to H'00005F
SCI3
23
IIC2
24
H'000060 to H'000063
A/D converter Timer Z0
25
H'000064 to H'000067 H'000068 to H'00006B H'00006C to H'00006F
Compare match/input capture A0 26 to D0 Overflow Compare match/input capture A1 27 to D1 Overflow Underflow Overflow Reserved for system use Receive data full Transmit data empty Transmit end Receive error 29 30, 31 32
Timer Z1
Timer B1 SCI3_2
H'000074 to H'000077 H'000078 to H'00007F H'000080 to H'000083 Low
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Section 3 Exception Handling
Relative Module SCI3_3
Exception Sources Reserved for system use Receive data full Transmit data empty Transmit end Receive error
Vector Number 33 34
Vector Address H'000084 to H'000087 H'000088 to H'00008B
Priority High
Low
Note:
*
A low-voltage detection interrupt is enabled only in the product with an on-chip poweron reset and low-voltage detection circuit.
3.2
Register Descriptions
Interrupts are controlled by the following registers. * * * * * * * Interrupt edge select register 1 (IEGR1) Interrupt edge select register 2 (IEGR2) Interrupt enable register 1 (IENR1) Interrupt enable register 2 (IENR2) Interrupt flag register 1 (IRR1) Interrupt flag register 2 (IRR2) Wakeup interrupt flag register (IWPR)
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Section 3 Exception Handling
3.2.1
Interrupt Edge Select Register 1 (IEGR1)
IEGR1 selects the direction of an edge that generates interrupt requests of pins NMI and IRQ3 to IRQ0.
Bit 7 Bit Name NMIEG Initial Value 0 R/W R/W Description NMI Edge Select 0: Falling edge of NMI pin input is detected 1: Rising edge of NMI pin input is detected 6 5 4 3 IEG3 1 1 1 0 R/W IRQ3 Edge Select 0: Falling edge of IRQ3 pin input is detected 1: Rising edge of IRQ3 pin input is detected 2 IEG2 0 R/W IRQ2 Edge Select 0: Falling edge of IRQ2 pin input is detected 1: Rising edge of IRQ2 pin input is detected 1 IEG1 0 R/W IRQ1 Edge Select 0: Falling edge of IRQ1 pin input is detected 1: Rising edge of IRQ1 pin input is detected 0 IEG0 0 R/W IRQ0 Edge Select 0: Falling edge of IRQ0 pin input is detected 1: Rising edge of IRQ0 pin input is detected Reserved These bits are always read as 1.
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Section 3 Exception Handling
3.2.2
Interrupt Edge Select Register 2 (IEGR2)
IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and WKP5 to WKP0.
Bit 7 6 5 Bit Name WPEG5 Initial Value 1 1 0 R/W R/W Description Reserved These bits are always read as 1. WKP5 Edge Select 0: Falling edge of WKP5(ADTRG) pin input is detected 1: Rising edge of WKP5(ADTRG) pin input is detected 4 WPEG4 0 R/W WKP4 Edge Select 0: Falling edge of WKP4 pin input is detected 1: Rising edge of WKP4 pin input is detected 3 WPEG3 0 R/W WKP3 Edge Select 0: Falling edge of WKP3 pin input is detected 1: Rising edge of WKP3 pin input is detected 2 WPEG2 0 R/W WKP2 Edge Select 0: Falling edge of WKP2 pin input is detected 1: Rising edge of WKP2 pin input is detected 1 WPEG1 0 R/W WKP1Edge Select 0: Falling edge of WKP1 pin input is detected 1: Rising edge of WKP1 pin input is detected 0 WPEG0 0 R/W WKP0 Edge Select 0: Falling edge of WKP0 pin input is detected 1: Rising edge of WKP0 pin input is detected
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Section 3 Exception Handling
3.2.3
Interrupt Enable Register 1 (IENR1)
IENR1 enables direct transition interrupts, RTC interrupts, and external pin interrupts.
Bit 7 Bit Name IENDT Initial Value 0 R/W R/W Description Direct Transfer Interrupt Enable When this bit is set to 1, direct transition interrupt requests are enabled. 6 IENTA 0 R/W RTC Interrupt Enable When this bit is set to 1, RTC interrupt requests are enabled. 5 IENWP 0 R/W Wakeup Interrupt Enable This bit is an enable bit, which is common to the pins WKP5 to WKP0. When the bit is set to 1, interrupt requests are enabled. 4 3 IEN3 1 0 R/W Reserved This bit is always read as 1. IRQ3 Interrupt Enable When this bit is set to 1, interrupt requests of the IRQ3 pin are enabled. 2 IEN2 0 R/W IRQ2 Interrupt Enable When this bit is set to 1, interrupt requests of the IRQ2 pin are enabled. 1 IEN1 0 R/W IRQ1 Interrupt Enable When this bit is set to 1, interrupt requests of the IRQ1 pin are enabled. 0 IEN0 0 R/W IRQ0 Interrupt Enable When this bit is set to 1, interrupt requests of the IRQ0 pin are enabled.
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear operations are performed while I = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception handling for the interrupt will be executed after the clear instruction has been executed.
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Section 3 Exception Handling
3.2.4
Interrupt Enable Register 2 (IENR2)
IENR2 enables, timer B1 overflow interrupts.
Bit 7 6 5 Bit Name IENTB1 Initial Value 0 0 0 R/W R/W Description Reserved These bits are always read as 0. Timer B1 Interrupt Enable When this bit is set to 1, timer B1 overflow interrupt requests are enabled. 4 3 2 1 0 1 1 1 1 1 Reserved These bits are always read as 1.
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear operations are performed while I = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception handling for the interrupt will be executed after the clear instruction has been executed.
3.2.5
Interrupt Flag Register 1 (IRR1)
IRR1 is a status flag register for direct transition interrupts, RTC interrupts, and IRQ3 to IRQ0 interrupt requests.
Bit 7 Bit Name IRRDT Initial Value 0 R/W R/W Description Direct Transfer Interrupt Request Flag [Setting condition] When a direct transfer is made by executing a SLEEP instruction while DTON in SYSCR2 is set to 1. [Clearing condition] When IRRDT is cleared by writing 0
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Section 3 Exception Handling
Bit 6
Bit Name IRRTA
Initial Value
R/W R/W
Description RTC Interrupt Request Flag [Setting condition] When the RTC counter value overflows [Clearing condition] When IRRTA is cleared by writing 0
5 4 3
IRRI3
1 1 0
R/W
Reserved These bits are always read as 1. IRQ3 Interrupt Request Flag [Setting condition] When IRQ3 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IRRI3 is cleared by writing 0
2
IRRI2
0
R/W
IRQ2 Interrupt Request Flag [Setting condition] When IRQ2 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IRRI2 is cleared by writing 0
1
IRRI1
0
R/W
IRQ1 Interrupt Request Flag [Setting condition] When IRQ1 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IRRI1 is cleared by writing 0
0
IRRl0
0
R/W
IRQ0 Interrupt Request Flag [Setting condition] When IRQ0 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IRRI0 is cleared by writing 0
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Section 3 Exception Handling
3.2.6
Interrupt Flag Register 2 (IRR2)
IRR2 is a status flag register for timer B1 overflow interrupts.
Bit 7 6 5 Bit Name IRRTB1 Initial Value 0 0 0 R/W R/W Description Reserved These bits are always read as 0. Timer B1 Interrupt Request flag [Setting condition] When the timer B1 counter value overflows [Clearing condition] When IRRTB1 is cleared by writing 0 4 3 2 1 0 1 1 1 1 1 Reserved These bits are always read as 1.
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Section 3 Exception Handling
3.2.7
Wakeup Interrupt Flag Register (IWPR)
IWPR is a status flag register for WKP5 to WKP0 interrupt requests.
Bit 7 6 5 Bit Name IWPF5 Initial Value 1 1 0 R/W R/W Description Reserved These bits are always read as 1. WKP5 Interrupt Request Flag [Setting condition] When WKP5 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF5 is cleared by writing 0. 4 IWPF4 0 R/W WKP4 Interrupt Request Flag [Setting condition] When WKP4 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF4 is cleared by writing 0. 3 IWPF3 0 R/W WKP3 Interrupt Request Flag [Setting condition] When WKP3 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF3 is cleared by writing 0. 2 IWPF2 0 R/W WKP2 Interrupt Request Flag [Setting condition] When WKP2 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF2 is cleared by writing 0. 1 IWPF1 0 R/W WKP1 Interrupt Request Flag [Setting condition] When WKP1 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF1 is cleared by writing 0. \
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Section 3 Exception Handling
Bit 0
Bit Name IWPF0
Initial Value 0
R/W R/W
Description WKP0 Interrupt Request Flag [Setting condition] When WKP0 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF0 is cleared by writing 0.
3.3
Reset Exception Handling
When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure that this LSI is reset at power-up, hold the RES pin low until the clock pulse generator output stabilizes. To reset the chip during operation, hold the RES pin low for at least 10 system clock cycles. When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling. The reset exception handling sequence is shown in figure 3.1. However, for the reset exception handling sequence of the product with on-chip power-on reset circuit, refer to section 20, Power-On Reset and Low-Voltage Detection Circuits (Optional). The reset exception handling sequence is as follows: 1. Set the I bit in the condition code register (CCR) to 1. 2. The CPU generates a reset exception handling vector address (from H'0000 to H'0001), the data in that address is sent to the program counter (PC) as the start address, and program execution starts from that address.
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Section 3 Exception Handling
3.4
3.4.1
Interrupt Exception Handling
External Interrupts
As the external interrupts, there are NMI, IRQ3 to IRQ0, and WKP5 to WKP0 interrupts. NMI Interrupt: NMI interrupt is requested by input signal edge to pin NMI. This interrupt is detected by either rising edge sensing or falling edge sensing, depending on the setting of bit NMIEG in IEGR1. NMI is the highest-priority interrupt, and can always be accepted without depending on the I bit value in CCR. IRQ3 to IRQ0 Interrupts: IRQ3 to IRQ0 interrupts are requested by input signals to pins IRQ3 to IRQ0. These four interrupts are given different vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG3 to IEG0 in IEGR1. When pins IRQ3 to IRQ0 are designated for interrupt input in PMR1 and the designated signal edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt. These interrupts can be masked by setting bits IEN3 to IEN0 in IENR1.
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Section 3 Exception Handling
WKP5 to WKP0 Interrupts: WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0. These six interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits WPEG5 to WPEG0 in IEGR2. When pins WKP5 to WKP0 are designated for interrupt input in PMR5 and the designated signal edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an interrupt. These interrupts can be masked by setting bit IENWP in IENR1.
Prefetch of first program instruction
Vector fetch
Internal processing
RES
Internal address bus
(1)
(3)
(5)
Internal read signal
Internal write signal Internal data bus (16 bits)
(2)
(4)
(6)
(1), (3) (2), (4) (5) (6)
Address of reset vector: (1) = H'000000, (3) = H'000002 Start address (contents of reset vector) Start address First instruction of program
Figure 3.1 Reset Sequence
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Section 3 Exception Handling
3.4.2
Internal Interrupts
Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the interrupt. For RTC interrupt requests and direct transfer interrupt requests generated by execution of a SLEEP instruction, this function is included in IRR1, IRR2, IENR1, and IENR2. When an on-chip peripheral module requests an interrupt, the corresponding interrupt request status flag is set to 1, requesting the CPU of an interrupt. These interrupts can be masked by writing 0 to clear the corresponding enable bit. 3.4.3 Interrupt Handling Sequence
Interrupts are controlled by an interrupt controller. Interrupt operation is described as follows. 1. If an interrupt occurs while the NMI or interrupt enable bit is set to 1, an interrupt request signal is sent to the interrupt controller. 2. When multiple interrupt requests are generated, the interrupt controller requests to the CPU for the interrupt handling with the highest priority at that time according to table 3.1. Other interrupt requests are held pending. 3. The CPU accepts the NMI and address break without depending on the I bit value. Other interrupt requests are accepted, if the I bit is cleared to 0 in CCR; if the I bit is set to 1, the interrupt request is held pending. 4. If the CPU accepts the interrupt after processing of the current instruction is completed, interrupt exception handling will begin. First, both PC and CCR are pushed onto the stack. The stack status at this time is shown in figure 3.2. The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. 5. Then, the I bit in CCR is set to 1, masking further interrupts excluding the NMI and address break. Upon return from interrupt handling, the values of I bit and other bits in CCR will be restored and returned to the values prior to the start of interrupt exception handling. 6. Next, the CPU generates the vector address corresponding to the accepted interrupt, and transfers the address to PC as a start address of the interrupt handling-routine. Then a program starts executing from the address indicated in PC.
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Section 3 Exception Handling
Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and the stack area is in the on-chip RAM.
SP - 4 SP - 3 SP - 2 SP - 1 SP (ER7) Stack area
SP (ER7) SP + 1 SP + 2 SP + 3 SP + 4
CCR PCE PCH PCL Even address
Prior to start of interrupt exception handling
PC and CCR saved to stack
After completion of interrupt exception handling
[Legend] PCE: Bits 23 to 16 of program counter (PC) PCH: Bits 15 to 8 of program counter (PC) PCL: Bits 7 to 0 of program counter (PC) CCR: Condition code register SP: Stack pointer Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt handling routine. 2. Register contents must always be saved and restored by word length, starting from an even-numbered address.
Figure 3.2 Stack Status after Exception Handling
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Section 3 Exception Handling
3.4.4
Interrupt Response Time
Table 3.2 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. Table 3.2
Item Interrupt priority determination Waiting time for completion of executing instruction* Saving of PC and CCR to stack Vector fetch Instruction fetch Internal processing
2
Interrupt Wait States
States 2*
1
Total 19 to 41
1 to 23 4 4 4 4
Notes: 1. In case of internal interrupts, the number of states is 1. 2. Not including EEPMOV instruction.
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REJ09B0060-0300
Internal processing Stack Vector fetch Internal processing Instruction prefetch of interrupt handling routine (1) (3) (5) (7) (9) (11) (13) High (2) (4) (6) (8) (10) (12) (14) (6), (8) PC and CCR saved to stack (9), (11) Vector address (10), (12) Starting address of interrupt handling routine (contents of vector address) Starting address of interrupt handling routine; (13) = (10), (12) (13) (14) First instruction of interrupt handling routine
Section 3 Exception Handling
Interrupt accepted Interrupt level Instruction decision and wait for prefetch end of instruction
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Interrupt request signal
Internal address bus
Internal read signal
Internal write signal
Figure 3.3 Interrupt Sequence
Internal data bus
(1)
Instruction prefetch address (not executed; return address, same as PC contents)
(2), (4) Instruction code (not executed) (3) Instruction prefetch address (not executed) (5) SP - 2 SP - 4 (7)
Section 3 Exception Handling
3.5
3.5.1
Usage Notes
Interrupts after Reset
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 3.5.2 Notes on Stack Area Use
When word data is accessed, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: ER7) should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @-SP) or POP Rn (MOV.W @SP+, Rn) to save or restore register values. 3.5.3 Notes on Rewriting Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins, IRQ3 to IRQ0, and WKP5 to WKP0, the interrupt request flag may be set to 1. When switching a pin function, mask the interrupt before setting the bit in the port mode register. After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0. Figure 3.4 shows a port mode register setting and interrupt request flag clearing procedure.
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Section 3 Exception Handling
CCR I bit 1
Interrupts masked. (Another possibility is to disable the relevant interrupt in interrupt enable register 1.)
Set port mode register bit Execute NOP instruction Clear interrupt request flag to 0 After setting the port mode register bit, first execute at least one instruction (e.g., NOP), then clear the interrupt request flag to 0.
CCR I bit 0
Interrupt mask cleared
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure
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Section 4 Address Break
Section 4 Address Break
The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address. With the address break function, the execution start point of a program containing a bug is detected and execution is branched to the correcting program. Figure 4.1 shows a block diagram of the address break.
Internal address bus
Comparator
BARE Interrupt generation control circuit
BARH
BARL ABRKCR ABRKSR Internal data bus Interrupt
BDRH
BDRL
Comparator
[Legend] BARE, BARH, BARL: Break address register BDRH, BDRL: Break data register ABRKCR: Address break control register ABRKSR: Address break status register
Figure 4.1 Block Diagram of Address Break
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Section 4 Address Break
4.1
Register Descriptions
The address break has the following registers. * * * * Address break control register (ABRKCR) Address break status register (ABRKSR) Break address registers E, H, L (BARE, BARH, BARL) Break data register (BDRH, BDRL) Address Break Control Register (ABRKCR)
4.1.1
ABRKCR sets address break conditions.
Bit 7 Bit Name RTINTE Initial Value 1 R/W R/W Description RTE Interrupt Enable When this bit is 0, the interrupt immediately after executing RTE is masked and then one instruction must be executed. When this bit is 1, the interrupt is not masked. 6 5 CSEL1 CSEL0 0 0 R/W R/W Condition Select 1 and 0 These bits set address break conditions. 00: Instruction execution cycle 01: CPU data read cycle 10: CPU data write cycle 11: CPU data read/write cycle 4 3 2 ACMP2 ACMP1 ACMP0 0 0 0 R/W R/W R/W Address Compare 2 to 0 These bits set the comparison condition between the address set in BAR and the internal address bus. 000: Compares 24-bit addresses 001: Compares upper 20-bit addresses 010: Compares upper 16-bit addresses 011: Compares upper 12-bit addresses 1xx: Reserved
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Section 4 Address Break
Bit 1 0
Bit Name DCMP1 DCMP0
Initial Value 0 0
R/W R/W R/W
Description Data Compare 1 and 0 These bits set the comparison condition between the data set in BDR and the internal data bus. 00: No data comparison 01: Compares lower 8-bit data between BDRL and data bus 10: Compares upper 8-bit data between BDRH and data bus 11: Compares 16-bit data between BDR and data bus
[Legend] x:
Don't care.
When an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of the byte/word access and address. Table 4.1 shows the access and data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a byte access is generated twice. For details on data widths of each register, see section 22.1, Register Addresses (Address Order). Table 4.1 Access and Data Bus Used
Word Access Odd Even Address Address ROM space RAM space I/O register with 8-bit data bus width I/O register with 16-bit data bus width Upper 8 bits Upper 8 bits Upper 8 bits Upper 8 bits Lower 8 bits Lower 8 bits Upper 8 bits Lower 8 bits Byte Access Even Address Odd Address Upper 8 bits Upper 8 bits Upper 8 bits -- Upper 8 bits Upper 8 bits Upper 8 bits --
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Section 4 Address Break
4.1.2
Address Break Status Register (ABRKSR)
ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.
Bit 7 Bit Name ABIF Initial Value 0 R/W R/W Description Address Break Interrupt Flag [Setting condition] When the condition set in ABRKCR is satisfied [Clearing condition] When 0 is written after ABIF=1 is read 6 ABIE 0 R/W Address Break Interrupt Enable When this bit is 1, an address break interrupt request is enabled. 5 to 0 All 1 Reserved These bits are always read as 1.
4.1.3
Break Address Registers E, H, L (BARE, BARH, BARL)
BAR (BARE, BARH, BARL) is a 24-bit readable/writable register that sets the address for generating an address break interrupt. The initial value of this register is H'FFFFFF. When setting the address break condition to the instruction execution cycle, set the first byte address of the instruction. 4.1.4 Break Data Registers H, L (BDRH, BDRL)
BDR (BDRH, BDRL) is a 16-bit readable/writable register that sets the data for generating an address break interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8-bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for even and odd addresses in the data transmission. Therefore, comparison data must be set in BDRH for byte access. For word access, the data bus used depends on the address. See section 4.1.1, Address Break Control Register (ABRKCR), for details. The initial value of this register is undefined.
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Section 4 Address Break
4.2
Operation
When the ABIE bit in ABRKSR is set to 1, if the ABIF bit in ABRKSR is set to 1 by the combination of the address set in BAR, the data set in BDR, and the conditions set in ABRKCR, the address break function generates an interrupt request to the CPU. When the interrupt request is accepted, interrupt exception handling starts after the instruction being executed ends. The address break interrupt is not masked because of the I bit in CCR of the CPU. Figures 4.2 (1) to (2) show the operation examples of the address break interrupt setting.
When the address break is specified in instruction execution cycle Register setting * ABRKCR = H'80 * BAR = H'025A Program 0258 * 025A 025C 0260 0262 :
NOP NOP MOV.W @H'025A,R0 NOP NOP :
Underline indicates the address to be stacked.
NOP MOV MOV NOP instruc- instruc- instruc- instruction tion 1 tion 2 Internal tion prefetch prefetch prefetch prefetch processing Address bus Interrupt request Interrupt acceptance 0258 025A 025C 025E
Stack save
SP-2
SP-4
Figure 4.2 Address Break Interrupt Operation Example (1)
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Section 4 Address Break
When the address break is specified in the data read cycle Register setting * ABRKCR = H'A0 * BAR = H'025A Program 0258 025A * 025C 0260 0262 :
NOP NOP MOV.W @H'025A,R0 NOP Underline indicates the address NOP to be stacked. :
MOV MOV NOP MOV NOP Next instruc- instruc- instruc- instruc- instruc- instrution 1 tion 2 tion tion tion ction Internal Stack prefetch prefetch prefetch execution prefetch prefetch processing save
Address bus Interrupt request
025C
025E
0260
025A
0262
0264
SP-2
Interrupt acceptance
Figure 4.2 Address Break Interrupt Operation Example (2)
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Section 5 Clock Pulse Generators
Section 5 Clock Pulse Generators
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator, a duty correction circuit, and system clock divider. The subclock pulse generator consists of a subclock oscillator and a subclock divider. Figure 5.1 shows a block diagram of the clock pulse generators.
OSC1 OSC2
System clock oscillator
OSC (fOSC)
Duty correction circuit
OSC (fOSC)
System clock divider
OSC OSC/8 OSC/16 OSC/32 OSC/64
/2 to /8192
System clock pulse generator
Prescaler S (13 bits)
W/2 X1 X2 Subclock oscillator W (fW) Subclock divider W/4 W/8 Prescaler W (5 bits) Subclock pulse generator SUB W/8 to W/128
Figure 5.1 Block Diagram of Clock Pulse Generators The basic clock signals that drive the CPU and on-chip peripheral modules are and SUB. The system clock is divided by prescaler S to become a clock signal from /8192 to /2, and the subclock is divided by prescaler W to become a clock signal from w/128 to w/8. Both the system clock and subclock signals are provided to the on-chip peripheral modules.
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Section 5 Clock Pulse Generators
5.1
System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing external clock input. Figure 5.2 shows a block diagram of the system clock generator.
OSC 2
LPM OSC 1 LPM: Low-power mode (standby mode, subactive mode, subsleep mode)
Figure 5.2 Block Diagram of System Clock Generator 5.1.1 Connecting Crystal Resonator
Figure 5.3 shows a typical method of connecting a crystal resonator. An AT-cut parallel-resonance crystal resonator should be used. Figure 5.4 shows the equivalent circuit of a crystal resonator. A resonator having the characteristics given in table 5.1 should be used.
C1 OSC 1 OSC 2 C2 C1 = C 2 = 10 to 22pF
Figure 5.3 Typical Connection to Crystal Resonator
LS RS
CS
OSC 1 C0
OSC 2
Figure 5.4 Equivalent Circuit of Crystal Resonator
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Section 5 Clock Pulse Generators
Table 5.1
Crystal Resonator Parameters
2 500 7 pF 4 120 7 pF 8 80 7 pF 10 60 7 pF 16 50 7 pF 20 40 7 pF
Frequency (MHz) RS (max.) C0 (max.)
5.1.2
Connecting Ceramic Resonator
Figure 5.5 shows a typical method of connecting a ceramic resonator.
C1 OSC1 C2 OSC2 C1 = 5 to 30pF C2 = 5 to 30pF
Figure 5.5 Typical Connection to Ceramic Resonator 5.1.3 External Clock Input Method
Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 5.6 shows a typical connection. The duty cycle of the external clock signal must be 45 to 55%.
OSC1
External clock input
OSC2
Open
Figure 5.6 Example of External Clock Input
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Section 5 Clock Pulse Generators
5.2
Subclock Generator
Figure 5.7 shows a block diagram of the subclock generator.
X2
8 M
X1 Note: Resistance is a reference value.
Figure 5.7 Block Diagram of Subclock Generator 5.2.1 Connecting 32.768-kHz Crystal Resonator
Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal resonator, as shown in figure 5.8. Figure 5.9 shows the equivalent circuit of the 32.768-kHz crystal resonator.
C1 X1 C2 X2 C1 = C 2 = 15 pF (typ.)
Figure 5.8 Typical Connection to 32.768-kHz Crystal Resonator
LS CS RS
X1 CO
X2
CO = 1.5 pF (typ.) RS = 14 k (typ.) fW = 32.768 kHz Note: Constants are reference values.
Figure 5.9 Equivalent Circuit of 32.768-kHz Crystal Resonator
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Section 5 Clock Pulse Generators
5.2.2
Pin Connection when not Using Subclock
When the subclock is not used, connect pin X1 to VCL or VSS and leave pin X2 open, as shown in figure 5.10.
VCL or VSS X1
X2
Open
Figure 5.10 Pin Connection when not Using Subclock
5.3
5.3.1
Prescalers
Prescaler S
Prescaler S is a 13-bit counter using the system clock () as its input clock. It is incremented once per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state. In standby mode, subactive mode, and subsleep mode, the system clock pulse generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write prescaler S. The output from prescaler S is shared by the on-chip peripheral modules. The divider ratio can be set separately for each on-chip peripheral function. In active mode and sleep mode, the clock input to prescaler S is determined by the division factor designated by the MA2 to MA0 bits in SYSCR2. 5.3.2 Prescaler W
Prescaler W is a 5-bit counter using a 32.768 kHz signal divided by 4 (W/4) as its input clock. The divided output is used for clock time base operation of timer A. Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state. Even in standby mode, subactive mode, or subsleep mode, prescaler W continues functioning so long as clock signals are supplied to pins X1 and X2.
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Section 5 Clock Pulse Generators
5.4
5.4.1
Usage Notes
Notes on Resonators
Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit constants will differ depending on the resonator element, stray capacitance in its interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the resonator element manufacturer. Design the circuit so that the resonator element never receives voltages exceeding its maximum rating. 5.4.2 Notes on Board Design
When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as close as possible to the OSC1 and OSC2 pins. Other signal lines should be routed away from the resonator circuit to prevent induction from interfering with correct oscillation (see figure 5.11).
Avoid Signal A Signal B C1 OSC1 C2 OSC2
Figure 5.11 Example of Incorrect Board Design
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Section 6 Power-Down Modes
Section 6 Power-Down Modes
This LSI has five modes of operation after a reset. These include a normal active mode and four power-down modes, in which power consumption is significantly reduced. The module standby function reduces power consumption by selectively halting on-chip module functions. * Active mode The CPU and all on-chip peripheral modules are operable on the system clock. The system clock frequency can be selected from osc, osc/8, osc/16, osc/32, and osc/64. * Subactive mode The CPU and all on-chip peripheral modules are operable on the subclock. The subclock frequency can be selected from w/2, w/4, and w/8. * Sleep mode The CPU halts. On-chip peripheral modules are operable on the system clock. * Subsleep mode The CPU halts. On-chip peripheral modules are operable on the subclock. * Standby mode The CPU and all on-chip peripheral modules halt. When the clock time-base function is selected, the RTC is operable. * Module standby function Independent of the above modes, power consumption can be reduced by halting on-chip peripheral modules that are not used in module units.
6.1
Register Descriptions
The registers related to power-down modes are listed below. For details on the serial mode control register (SCI3_3 module standby), see section 17, Serial Communication Interface 3 (SCI3). * * * * * System control register 1 (SYSCR1) System control register 2 (SYSCR2) Module standby control register 1 (MSTCR1) Module standby control register 2 (MSTCR2) Serial Mode Control Register (SMCR)
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Section 6 Power-Down Modes
6.1.1
System Control Register 1 (SYSCR1)
SYSCR1 controls the power-down modes, as well as SYSCR2.
Bit 7 Bit Name SSBY Initial Value 0 R/W R/W Description Software Standby This bit selects the mode to transit after the execution of the SLEEP instruction. 0: Enters sleep mode or subsleep mode. 1: Enters standby mode. For details, see table 6.2. 6 5 4 STS2 STS1 STS0 0 0 0 R/W R/W R/W Standby Timer Select 2 to 0 These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode, subactive mode, or subsleep mode to active mode or sleep mode due to an interrupt. The designation should be made according to the clock frequency so that the waiting time is at least 6.5 ms. The relationship between the specified value and the number of wait states is shown in table 6.1. When an external clock is to be used, the minimum value (STS2 = STS1 = STS0 =1) is recommended. Noise Elimination Sampling Frequency Select The subclock pulse generator generates the watch clock signal (W) and the system clock pulse generator generates the oscillator clock (OSC). This bit selects the sampling frequency of the oscillator clock when the watch clock signal (W) is sampled. When OSC = 4 to 20 MHz, clear NESEL to 0. 0: Sampling rate is OSC/16 1: Sampling rate is OSC/4 2 1 0 0 0 0 Reserved These bits are always read as 0.
3
NESEL
0
R/W
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Section 6 Power-Down Modes
Table 6.1
Operating Frequency and Waiting Time
Operating Frequency 20 MHz 16 MHz 0.4 0.8 1.6 3.3 6.6 0.05 0.00 0.00 0.5 1.0 2.0 4.1 8.2 0.06 0.00 0.00 10 MHz 8 MHz 4 MHz 2 MHz 1 MHz 0.5 MHz 0.8 1.6 3.3 6.6 13.1 0.10 0.01 0.00 1.0 2.0 4.1 8.2 16.4 0.13 0.02 0.00 2.0 4.1 8.2 16.4 32.8 0.26 0.03 0.00 4.1 8.2 16.4 32.8 65.5 0.51 0.06 0.01 8.1 16.4 32.8 65.5 16.4 32.8 65.5 131.1
Bit Name STS2 STS1 STS0 Waiting Time 0 0 0 1 1 0 1 1 0 0 1 1 0 1 8,192 states 16,384 states 32,768 states 65,536 states 131,072 states 1,024 states 128 states 16 states
131.1 262.1 1.02 0.13 0.02 2.05 0.26 0.03
Note: Time unit is ms.
6.1.2
System Control Register 2 (SYSCR2)
SYSCR2 controls the power-down modes, as well as SYSCR1.
Bit 7 6 5 Bit Name SMSEL LSON DTON Initial Value 0 0 0 R/W R/W R/W R/W Description Sleep Mode Selection Low Speed on Flag Direct Transfer on Flag These bits select the mode to enter after the execution of a SLEEP instruction, as well as bit SSBY of SYSCR1. For details, see table 6.2. 4 3 2 MA2 MA1 MA0 0 0 0 R/W R/W R/W Active Mode Clock Select 2 to 0 These bits select the operating clock frequency in active and sleep modes. The operating clock frequency changes to the set frequency after the SLEEP instruction is executed. 0xx: OSC 100: OSC/8 101: OSC/16 110: OSC/32 111: OSC/64
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Section 6 Power-Down Modes
Bit 1 0
Bit Name SA1 SA0
Initial Value 0 0
R/W R/W R/W
Description Subactive Mode Clock Select 1 and 0 These bits select the operating clock frequency in subactive and subsleep modes. The operating clock frequency changes to the set frequency after the SLEEP instruction is executed. 00: W/8 01: W/4 1x: W/2
[Legend]
x:
Don't care.
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Section 6 Power-Down Modes
6.1.3
Module Standby Control Register 1 (MSTCR1)
MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units.
Bit 7 6 5 4 Bit Name MSTIIC MSTS3 MSTAD Initial Value 0 0 0 0 R/W R/W R/W R/W Description Reserved This bit is always read as 0. IIC2 Module Standby IIC2 enters standby mode when this bit is set to 1 SCI3 Module Standby SCI3 enters standby mode when this bit is set to 1 A/D Converter Module Standby A/D converter enters standby mode when this bit is set to 1 3 MSTWD 0 R/W Watchdog Timer Module Standby Watchdog timer enters standby mode when this bit is set to 1.When the internal oscillator is selected for the watchdog timer clock, the watchdog timer operates regardless of the setting of this bit 2 1 0 MSTTW MSTTV MSTTA 0 0 0 R/W R/W R/W Timer W Module Standby Timer W enters standby mode when this bit is set to 1 Timer V Module Standby Timer V enters standby mode when this bit is set to 1 RTC Module Standby RTC enters standby mode when this bit is set to 1
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Section 6 Power-Down Modes
6.1.4
Module Standby Control Register 2 (MSTCR2)
MSTCR2 allows the on-chip peripheral modules to enter a standby state in module units.
Bit 7 6 5 4 3 2 1 0 Bit Name MSTS3_2 MSTTB1 MSTTZ MSTPWM Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W Description SCI3_2 Module Standby SCI3_2 enters standby mode when this bit is set to1 Reserved These bits are always read as 0. Timer B1 Module Standby Timer B1 enters standby mode when this bit is set to1 Reserved These bits are always read as 0. Timer Z Module Standby Timer Z enters standby mode when this bit is set to1 PWM Module Standby PWM enters standby mode when this bit is set to1
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Section 6 Power-Down Modes
6.2
Mode Transitions and States of LSI
Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state by executing a SLEEP instruction. Interrupts allow for returning from the program halt state to the program execution state. A direct transition between active mode and subactive mode, which are both program execution states, can be made without halting the program. The operating frequency can also be changed in the same modes by making a transition directly from active mode to active mode, and from subactive mode to subactive mode. RES input enables transitions from a mode to the reset state. Table 6.2 shows the transition conditions of each mode after the SLEEP instruction is executed and a mode to return by an interrupt. Table 6.3 shows the internal states of the LSI in each mode.
Reset state Program halt state Program execution state Direct transition interrupt SLEEP instruction Interrupt Program halt state
SLEEP instruction Standby mode Interrupt Active mode
Sleep mode
SLEEP instruction Direct transition interrupt SLEEP instruction SLEEP instruction Interrupt Direct transition interrupt Interrupt
SLEEP instruction Subactive mode Subsleep mode Interrupt
Direct transition interrupt Notes: 1. To make a transition to another mode by an interrupt, make sure interrupt handling is after the interrupt is accepted. 2. Details on the mode transition conditions are given in table 6.2.
Figure 6.1 Mode Transition Diagram
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Section 6 Power-Down Modes
Table 6.2
Transition Mode after SLEEP Instruction Execution and Transition Mode due to Interrupt
Transition Mode after SLEEP Instruction Execution Sleep mode Transition Mode due to Interrupt Active mode Subactive mode Subsleep mode Active mode Subactive mode Standby mode Active mode (direct transition) Subactive mode (direct transition) Active mode -- --
DTON 0
SSBY 0
SMSEL 0
LSON 0 1
1
0 1
1 1 X X [Legend] *
X 0* X
X 0 1
X: Don't care. When a state transition is performed while SMSEL is 1, timer V, SCI3, SCI3_2, SCI3_3, and the A/D converter are reset, and all registers are set to their initial values. To use these functions after entering active mode, reset the registers.
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Section 6 Power-Down Modes
Table 6.3
Function
Internal State in Each Operating Mode
Active Mode Functioning Functioning Functioning Functioning Functioning Functioning Sleep Mode Functioning Functioning Halted Retained Retained Retained Subactive Mode Halted Functioning Functioning Functioning Functioning Functioning Subsleep Mode Halted Functioning Halted Retained Retained Retained Standby Mode Halted Functioning Halted Retained Retained Register contents are retained, but output is the highimpedance state. Functioning Functioning
System clock oscillator Subclock oscillator CPU Instructions operations Registers RAM IO ports
External interrupts
IRQ3 to IRQ0 WKP5 to WKP0
Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning
Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning
Functioning Functioning
Functioning Functioning
Peripheral RTC functions Timer V Watchdog timer SCI3, SCI3_2, SCI3_3 IIC2 Timer B1 Timer Z Timer W
Functioning if the timekeeping time-base function is selected, and retained if not selected Reset Reset Reset
Retained (functioning if the internal oscillator is selected as a count clock*) Reset Retained* Retained* Retained* Reset Retained Retained Retained Reset Retained Retained Retained Retained
Retained (the counter is incremented by a subclock if the internal clock is selected as a count clock*) Reset Reset
A/D converter
Functioning
Functioning
Reset
Note:
*
Registers can be read or written in subactive mode.
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Section 6 Power-Down Modes
6.2.1
Sleep Mode
In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2, MA1, and MA0 bits in SYSCR2. CPU register contents are retained. When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the requested interrupt is disabled in the interrupt enable register. After sleep mode is cleared, a transition is made to active mode when the LSON bit in SYSCR2 is 0, and a transition is made to subactive mode when the bit is 1. When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared. 6.2.2 Standby Mode
In standby mode, the clock pulse generator stops, so the CPU and on-chip peripheral modules stop functioning. However, as long as the rated voltage is supplied, the contents of CPU registers, onchip RAM, and some on-chip peripheral module registers are retained. On-chip RAM contents will be retained as long as the voltage set by the RAM data retention voltage is provided. The I/O ports go to the high-impedance state. Standby mode is cleared by an interrupt. When an interrupt is requested, the system clock pulse generator starts. After the time set in bits STS2 to STS0 in SYSCR1 has elapsed, and interrupt exception handling starts. Standby mode is not cleared if the I bit of CCR is set to 1 or the requested interrupt is disabled in the interrupt enable register. When the RES pin goes low, the system clock pulse generator starts. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
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Section 6 Power-Down Modes
6.2.3
Subsleep Mode
In subsleep mode, operation of the CPU and on-chip peripheral modules other than RTC is halted. As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM, and some registers of the on-chip peripheral modules are retained. I/O ports keep the same states as before the transition. Subsleep mode is cleared by an interrupt. When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. Subsleep mode is not cleared if the I bit of CCR is set to 1 or the requested interrupt is disabled in the interrupt enable register. After subsleep mode is cleared, a transition is made to active mode when the LSON bit in SYSCR2 is 0, and a transition is made to subactive mode when the bit is 1. After the time set in bits STS2 to STS0 in SYSCR1 has elapsed, a transition is made to active mode. When the RES pin goes low, the system clock pulse generator starts. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator output has stabilized, the CPU starts reset exception handling if the RES pin is driven high. 6.2.4 Subactive Mode
The operating frequency of subactive mode is selected from W/2, W/4, and W/8 by the SA1 and SA0 bits in SYSCR2. After the SLEEP instruction is executed, the operating frequency changes to the frequency which is set before the execution. When the SLEEP instruction is executed in subactive mode, a transition to sleep mode, subsleep mode, standby mode, active mode, or subactive mode is made, depending on the combination of SYSCR1 and SYSCR2. When the RES pin goes low, the system clock pulse generator starts. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
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Section 6 Power-Down Modes
6.3
Operating Frequency in Active Mode
Operation in active mode is clocked at the frequency designated by the MA2, MA1, and MA0 bits in SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction execution.
6.4
Direct Transition
The CPU can execute programs in two modes: active and subactive modes. A direct transition is a transition between these two modes without stopping program execution. A direct transition can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. The direct transition also enables operating frequency modification in active or subactive mode. After the mode transition, direct transition interrupt exception handling starts. If the direct transition interrupt is disabled in interrupt enable register 1, a transition is made instead to sleep or subsleep mode. Note that if a direct transition is attempted while the I bit in CCR is set to 1, sleep or subsleep mode will be entered, and the resulting mode cannot be cleared by means of an interrupt. 6.4.1 Direct Transition from Active Mode to Subactive Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (1). Direct transition time = {(number of SLEEP instruction execution states) + (number of internal processing states)}x (tcyc before transition) + (number of interrupt exception handling states) x (tsubcyc after transition) (1) Example:
Direct transition time = (2 + 1) x tosc + 16 x 8 tw = 3 tosc + 128 tw (when the CPU operating clock of osc w/8 is selected)
[Legend] tosc: tw: tcyc: tsubcyc:
OSC clock cycle time Watch clock cycle time System clock () cycle time Subclock (SUB) cycle time
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Section 6 Power-Down Modes
6.4.2
Direct Transition from Subactive Mode to Active Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2). Direct transition time = {(number of SLEEP instruction execution states) + (number of internal processing states)} x (tsubcyc before transition) + {(waiting time set in bits STS2 to STS0) + (number of interrupt exception handling states)} x (tcyc after transition) (2) Example:
Direct transition time = (2 + 1) x 8 tw + (8192 + 16) x tosc = 24 tw + 8208 tosc (when the CPU operating clock of w/8 osc and a waiting time of 8192 states are selected)
[Legend] tosc: tw: tcyc: tsubcyc:
OSC clock cycle time Watch clock cycle time System clock () cycle time Subclock (SUB) cycle time
6.5
Module Standby Function
The module-standby function can be set to any peripheral module. In the module standby state, the clock supply to modules stops to enter the power-down mode. Setting a bit in MSTCR1, MSTCR2, or SMCR that corresponds to each module to 1 enables each on-chip peripheral module to enter the module standby state and the module standby state is canceled by clearing the bit to 0.
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Section 6 Power-Down Modes
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Section 7 ROM
Section 7 ROM
The features of the 96-kbyte flash memory built into the flash memory (F-ZTAT) version are summarized below. * Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is configured as follows: 1 kbyte x 4 blocks, 28 kbytes x 1 block, 16 kbytes x 2 blocks, and 32 kbytes x 1 block for H8/36049F. To erase the entire flash memory, each block must be erased in turn. * Reprogramming capability The flash memory can be reprogrammed up to 1,000 times. * On-board programming On-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. In normal user program mode, individual blocks can be erased or programmed. * Programmer mode Flash memory can be programmed/erased in programmer mode using a PROM programmer, as well as in on-board programming mode. * Automatic bit rate adjustment For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. * Programming/erasing protection Sets software protection against flash memory programming/erasing. * Power-down mode Operation of the power supply circuit can be partly halted in subactive mode. As a result, flash memory can be read with low power consumption.
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Section 7 ROM
7.1
Block Configuration
Figure 7.1 shows the block configuration of flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The 96-kbyte flash memory is divided into 1 kbyte x 4 blocks, 28 kbytes x 1 block, 16 kbytes x 2 blocks, and 32 kbytes x 1 block. Erasing is performed in these units. Programming is performed in 128-byte units starting from an address with lower eight bits H'00 or H'80.
H'000000 Erase unit: 1 kbyte Erase unit: 1 kbyte Erase unit: 1 kbyte Erase unit: 1 kbyte Erase unit: 28 kbytes H'007F80 Erase unit: 16 kbytes H'008000 H'000780 H'000800 H'000380 H'000400
H'000001 H'000381 H'000401
H'000002 H'000382 H'000402
Programming unit: 128 bytes
H'00007F H'0003FF
Programming unit: 128 bytes
H'00047F H'0007FF
H'000781 H'000801
H'000782 H'000802 H'000B82 H'000C02 Programming unit: 128 bytes Programming unit: 128 bytes
H'00087F
H'000B80 H'000B81 H'000C00 H'000C01
H'000BFF H'000C7F H'000FFF Programming unit: 128 bytes H'00107F H'007FFF Programming unit: 128 bytes H'00807F H'00BFFF Programming unit: 128 bytes H'00C07F H'00FFFF Programming unit: 128 bytes H'01007F H'017FFF
H'000F80 H'001000
H'000F81 H'001001 H'007F81 H'008001
H'000F82 H'001002 H'007F82 H'008002 H'00BF82 H'00C002
H'00BF80 H'00BF81 Erase unit: 16 kbytes H'00FF80 H'00FF81 Erase unit: 32 kbytes H'017F80 H'017F81 H'010000 H'010001 H'00C000 H'00C001
H'00FF82 H'010002 H'017F82
Figure 7.1 Block Configuration of Flash Memory
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Section 7 ROM
7.2
Register Descriptions
The flash memory has the following registers. * * * * * Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Erase block register 1 (EBR1) Flash memory power control register (FLPWCR) Flash memory enable register (FENR) Flash Memory Control Register 1 (FLMCR1)
7.2.1
FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 7.4, Flash Memory Programming/Erasing.
Bit 7 6 Bit Name -- SWE Initial Value 0 0 R/W -- R/W Description Reserved This bit is always read as 0. Software Write Enable When this bit is set to 1, flash memory programming/erasing is enabled. When this bit is cleared to 0, other FLMCR1 register bits and all EBR1 bits cannot be set. 5 ESU 0 R/W Erase Setup When this bit is set to 1, the flash memory changes to the erase setup state. When it is cleared to 0, the erase setup state is cancelled. Set this bit to 1 before setting the E bit to 1 in FLMCR1. 4 PSU 0 R/W Program Setup When this bit is set to 1, the flash memory changes to the program setup state. When it is cleared to 0, the program setup state is cancelled. Set this bit to 1 before setting the P bit in FLMCR1. 3 EV 0 R/W Erase-Verify When this bit is set to 1, the flash memory changes to erase-verify mode. When it is cleared to 0, erase-verify mode is cancelled.
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Section 7 ROM
Bit 2
Bit Name PV
Initial Value 0
R/W R/W
Description Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, programverify mode is cancelled.
1
E
0
R/W
Erase When this bit is set to 1 while SWE=1 and ESU=1, the flash memory changes to erase mode. When it is cleared to 0, erase mode is cancelled.
0
P
0
R/W
Program When this bit is set to 1 while SWE=1 and PSU=1, the flash memory changes to program mode. When it is cleared to 0, program mode is cancelled.
7.2.2
Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to.
Bit 7 Bit Name FLER Initial Value 0 R/W R Description Flash Memory Error Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state. See section 7.5.3, Error Protection, for details. 6 to 0 -- All 0 -- Reserved These bits are always read as 0.
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Section 7 ROM
7.2.3
Erase Block Register 1 (EBR1)
EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to be automatically cleared to 0.
Bit 7 6 5 4 3 2 1 0 Bit Name EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When this bit is set to 1, 32 kbytes of H'010000 to H'017FFF will be erased. When this bit is set to 1, 16 kbytes of H'00C000 to H'00FFFF will be erased. When this bit is set to 1, 16 kbytes of H'008000 to H'00BFFF will be erased. When this bit is set to 1, 28 kbytes of H'001000 to H'007FFF will be erased. When this bit is set to 1, 1 kbyte of H'000C00 to H'000FFF will be erased. When this bit is set to 1, 1 kbyte of H'000800 to H'000BFF will be erased. When this bit is set to 1, 1 kbyte of H'000400 to H'0007FF will be erased. When this bit is set to 1, 1 kbyte of H'000000 to H'0003FF will be erased.
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Section 7 ROM
7.2.4
Flash Memory Power Control Register (FLPWCR)
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. There are two modes: mode in which operation of the power supply circuit of flash memory is partly halted in power-down mode and flash memory can be read, and mode in which even if a transition is made to subactive mode, operation of the power supply circuit of flash memory is retained and flash memory can be read.
Bit 7 Bit Name PDWND Initial Value 0 R/W R/W Description Power-Down Disable When this bit is 0 and a transition is made to subactive mode, the flash memory enters the power-down mode. When this bit is 1, the flash memory remains in the normal mode even after a transition is made to subactive mode. 6 to 0 -- All 0 -- Reserved These bits are always read as 0.
7.2.5
Flash Memory Enable Register (FENR)
Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR1, and FLPWCR.
Bit 7 Bit Name FLSHE Initial Value 0 R/W R/W Description Flash Memory Control Register Enable Flash memory control registers can be accessed when this bit is set to 1. Flash memory control registers cannot be accessed when this bit is set to 0. 6 -- 0 R/W Reserved This bit can be read from or written to, but should not be set to 1. 5 to 0 -- All 0 -- Reserved These bits are always read as 0.
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Section 7 ROM
7.3
On-Board Programming Modes
There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST pin settings, NMI pin settings, and input level of each port, as shown in table 7.1. The input level of each pin must be defined four states before the reset ends. When changing to boot mode, the boot program built into this LSI is initiated. The boot program transfers the programming control program from the externally-connected host to on-chip RAM via SCI3. After erasing the entire flash memory, the programming control program is executed. This can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. In user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. Table 7.1
TEST 0 0 1 [Legend]
Setting Programming Modes
NMI 1 0 X P85 X 1 X X : Don't care. PB0 X X 0 PB1 X X 0 PB2 X X 0 LSI State after Reset End User Mode Boot Mode Programmer Mode
7.3.1
Boot Mode
Table 7.2 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 7.4, Flash Memory Programming/Erasing. 2. SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity.
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Section 7 ROM
3. When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be pulled up on the board if necessary. After the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the completion of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could not be performed normally, initiate boot mode again by a reset. Depending on the host's transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate and system clock frequency of this LSI within the ranges listed in table 7.3. 5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'FFF780 to H'FFFEEF is the area to which the programming control program is transferred from the host. The boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. Before branching to the programming control program, the chip terminates transfer operations by SCI3 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value remains set in BRR. Therefore, the programming control program can still use it for transfer of program data or verify data with the host. The TxD pin is high (PCR22 = 1, P22 = 1). The contents of the CPU general registers are undefined immediately after branching to the programming control program. These registers must be initialized at the beginning of the programming control program, as the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc. 7. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at least 20 states, and then setting the TEST pin and NMI pin. Boot mode is also cleared when a WDT overflow occurs. 8. Do not change the TEST pin and NMI pin input levels in boot mode.
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Section 7 ROM
Table 7.2
Item
Boot Mode Operation
Host Operation Processing Contents Communication Contents LSI Operation Processing Contents Branches to boot program at reset-start.
Boot mode initiation
Boot program initiation
Bit rate adjustment
Continuously transmits data H'00 at specified bit rate.
H'00, H'00 . . . H'00
Transmits data H'55 when data H'00 is received error-free.
H'00 H'55
* Measures low-level period of receive data H'00. * Calculates bit rate and sets BRR in SCI3. * Transmits data H'00 to host as adjustment end indication. H'55 reception
Flash memory erase
Boot program erase error
H'FF
H'AA reception
H'AA
Checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data H'AA to host. (If erase could not be done, transmits data H'FF to host and aborts operation.)
Transfer of number of bytes of programming control program
Transmits number of bytes (N) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte)
Upper bytes, lower bytes Echoback
Echobacks the 2-byte data received to host.
Transmits 1-byte of programming control program (repeated for N times)
H'XX Echoback
Echobacks received data to host and also transfers it to RAM. (repeated for N times)
H'AA reception
H'AA
Transmits data H'AA to host.
Branches to programming control program transferred to on-chip RAM and starts execution.
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Section 7 ROM
Table 7.3
System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible
System Clock Frequency Range of LSI 16 to 20 MHz 8 to 16 MHz 4 to 16 MHz 2 to 16 MHz
Host Bit Rate 19,200 bps 9,600 bps 4,800 bps 2,400 bps
7.3.2
Programming/Erasing in User Program Mode
On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. As the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot mode. Figure 7.2 shows a sample procedure for programming/erasing in user program mode. Prepare a user program/erase control program in accordance with the description in section 7.4, Flash Memory Programming/Erasing.
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Reset-start
No Program/erase? Yes Transfer user program/erase control program to RAM Branch to flash memory application program
Branch to user program/erase control program in RAM
Execute user program/erase control program (flash memory rewrite)
Branch to flash memory application program
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode
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Section 7 ROM
7.4
Flash Memory Programming/Erasing
A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. Flash memory programming and erasing should be performed in accordance with the descriptions in section 7.4.1, Program/Program-Verify and section 7.4.2, Erase/Erase-Verify, respectively. 7.4.1 Program/Program-Verify
When writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 7.3 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. Programming must be done to an empty address. Do not reprogram an address to which programming has already been performed. 2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform reprogramming data computation according to table 7.4, and additional programming data computation according to table 7.5. 4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The program address and 128-byte data are latched in the flash memory. The lower 8 bits of the start address in the flash memory destination area must be H'00 or H'80. 5. The time during which the P bit is set to 1 is the programming time. Table 7.6 shows the allowable programming times. 6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. An overflow cycle of approximately 6.6 ms is allowed. 7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits are B'00. Verify data can be read in words or in longwords from the address to which a dummy write was performed.
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8.
The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000.
Write pulse application subroutine
Apply Write Pulse WDT enable Set PSU bit in FLMCR1 Wait 50 s Set P bit in FLMCR1 Wait (Wait time=programming time) Clear P bit in FLMCR1 Wait 5 s Clear PSU bit in FLMCR1 Wait 5 s
Disable WDT
START Set SWE bit in FLMCR1 Wait 1 s
*
Store 128-byte program data in program data area and reprogram data area
n= 1 m= 0
Write 128-byte data in RAM reprogram data area consecutively to flash memory
Apply Write pulse Set PV bit in FLMCR1 Wait 4 s Set block start address as verify address
nn+1 H'FF dummy write to verify address
Wait 2 s
Read verify data Increment address Verify data = write data?
*
No m=1
Yes n6? No
Yes Additional-programming data computation
Reprogram data computation
No
128-byte data verification completed?
Yes Clear PV bit in FLMCR1 Wait 2 s n 6? Yes Successively write 128-byte data from additionalprogramming data area in RAM to flash memory Sub-Routine-Call Apply Write Pulse No Yes No
m= 0 ? Yes Clear SWE bit in FLMCR1 Wait 100 s
End of programming
n 1000 ?
No Clear SWE bit in FLMCR1 Wait 100 s
Programming failure
Note: * The RTS instruction must not be used during the following 1. and 2. periods. 1. A period between 128-byte data programming to flash memory and the P bit clearing 2. A period between dummy writing of H'FF to a verify address and verify data reading
Figure 7.3 Program/Program-Verify Flowchart
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Table 7.4
Reprogram Data Computation Table
Verify Data 0 1 0 1 Reprogram Data 1 0 1 1 Comments Programming completed Reprogram bit -- Remains in erased state
Program Data 0 0 1 1
Table 7.5
Additional-Program Data Computation Table
Verify Data 0 1 0 1 Additional-Program Data 0 1 1 1 Comments Additional-program bit No additional programming No additional programming No additional programming
Reprogram Data 0 0 1 1
Table 7.6
Programming Time
In Additional Programming 10 -- Comments
n Programming (Number of Writes) Time 1 to 6 7 to 1,000 30 200
Note: Time shown in s.
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Section 7 ROM
7.4.2
Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR1). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An overflow cycle of approximately 19.8 ms is allowed. 5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two bits are B'00. Verify data can be read in longwords from the address to which a dummy write was performed. 6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is 100. 7.4.3 Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. Interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. If interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the CPU malfunctions. 3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out.
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Erase start SWE bit 1 Wait 1 s n1 Set EBR1 Enable WDT ESU bit 1 Wait 100 s E bit 1 Wait 10 ms E bit 0 Wait 10 s ESU bit 10 10 s Disable WDT EV bit 1 Wait 20 s
Set block start address as verify address
H'FF dummy write to verify address Wait 2 s Read verify data No Increment address Verify data + all 1s ? Yes No Last address of block ? Yes EV bit 0 Wait 4 s EV bit 0 Wait 4s
*
nn+1
No
All erase block erased ? Yes Yes SWE bit 0 Wait 100 s End of erasing
n 100 ? No
Yes
SWE bit 0 Wait 100 s Erase failure
Note: * The RTS instruction must not be used during a period between dummy writing of H'FF to a verify address and verify data reading.
Figure 7.4 Erase/Erase-Verify Flowchart
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Section 7 ROM
7.5
Program/Erase Protection
There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), and erase block register 1 (EBR1) are initialized. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. 7.5.2 Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block register 1 (EBR1), erase protection can be set for individual blocks. When EBR1 is set to H'00, erase protection is set for all blocks. 7.5.3 Error Protection
In error protection, an error is detected when CPU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is forcibly aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. When the following errors are detected during programming/erasing of flash memory, the FLER bit in FLMCR2 is set to 1, and the error protection state is entered. * When the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) * Immediately after exception handling excluding a reset during programming/erasing * When a SLEEP instruction is executed during programming/erasing
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The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be reentered by re-setting the P or E bit. However, PV and EV bit settings are retained, and a transition can be made to verify mode. Error protection can be cleared only by a power-on reset.
7.6
Programmer Mode
In programmer mode, a PROM programmer can be used to perform programming/erasing via a socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU device type with the on-chip Renesas Technology 128-kbyte flash memory.
7.7
Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states: * Normal operating mode The flash memory can be read and written to at high speed. * Power-down operating mode The power supply circuit of flash memory can be partly halted. As a result, flash memory can be read with low power consumption. * Standby mode All flash memory circuits are halted. Table 7.7 shows the correspondence between the operating modes of this LSI and the flash memory. In subactive mode, the flash memory can be set to operate in power-down mode with the PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from power-down mode or standby mode, a period to stabilize operation of the power supply circuits that were stopped is needed. When the flash memory returns to its normal operating state, bits STS2 to STS0 in SYSCR1 must be set to provide a wait time of at least 20 s, even when the external clock is being used.
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Section 7 ROM
Table 7.7
Flash Memory Operating States
Flash Memory Operating State
LSI Operating State Active mode Subactive mode Sleep mode Subsleep mode Standby mode
PDWND = 0 (Initial Value) Normal operating mode Power-down mode Normal operating mode Standby mode Standby mode
PDWND = 1 Normal operating mode Normal operating mode Normal operating mode Standby mode Standby mode
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Section 8 RAM
Section 8 RAM
This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data.
Product Classification Flash memory version (F-ZTATTM version) Masked ROM version H8/36049F H8/36049 H8/36048 H8/36047 Note: * RAM Size 4 kbytes 3 kbytes 3 kbytes 3 kbytes RAM Address H'FFE800 to H'FFEFFF, H'FFF780 to H'FFFF7F* H'FFE800 to H'FFEFFF, H'FFFB80 to H'FFFF7F H'FFE800 to H'FFEFFF, H'FFFB80 to H'FFFF7F H'FFE800 to H'FFEFFF, H'FFFB80 to H'FFFF7F
When the E7 or E8 is used, area H'FFF780 to H'FFFB7F must not be accessed.
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Section 8 RAM
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Section 9 I/O Ports
Section 9 I/O Ports
The group of this LSI has fifty-nine general I/O ports and eight general input-only ports. Thirteen ports are large current ports, which can drive 20 mA (@VOL = 1.5 V) when a low level signal is output. Any of these ports can become an input port immediately after a reset. They can also be used as I/O pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings. The registers for selecting these functions can be divided into two types: those included in I/O ports and those included in each onchip peripheral module. General I/O ports are comprised of the port control register for controlling inputs/outputs and the port data register for storing output data and can select inputs/outputs in bit units. For functions in each port, see appendix B.1, I/O Port Block Diagrams. For the execution of bitmanipulation instructions to the port control register and port data register, see section 2.8.3, Bit Manipulation Instruction.
9.1
Port 1
Port 1 is a general I/O port also functioning as IRQ interrupt input pins, an RTC output pin, a 14bit PWM output pin, a timer B1 input pin, and a timer V input pin. Figure 9.1 shows its pin configuration.
P17/IRQ3/TRGV P16/IRQ2 P15/IRQ1/TMIB1 Port 1 P14/IRQ0 P12 P11/PWM P10/TMOW
Figure 9.1 Port 1 Pin Configuration Port 1 has the following registers. * * * * Port mode register 1 (PMR1) Port control register 1 (PCR1) Port data register 1 (PDR1) Port pull-up control register 1 (PUCR1)
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9.1.1
Port Mode Register 1 (PMR1)
PMR1 switches the functions of pins in port 1 and port 2.
Bit 7 Bit Name IRQ3 Initial Value 0 R/W R/W Description Selects the function of pin P17/IRQ3/TRGV. 0: General I/O port 1: IRQ3/TRGV input pin 6 IRQ2 0 R/W Selects the function of pin P16/IRQ2. 0: General I/O port 1: IRQ2 input pin 5 IRQ1 0 R/W Selects the function of pin P15/IRQ1/TMIB1. 0: General I/O port 1: IRQ1/TMIB1 input pin 4 IRQ0 0 R/W Selects the function of pin P14/IRQ0. 0: General I/O port 1: IRQ0 input pin 3 TXD2 0 R/W Selects the function of pin P72/TXD_2. 0: General I/O port 1: TXD_2 output pin 2 PWM 0 R/W Selects the function of pin P11/PWM. 0: General I/O port 1: PWM output pin 1 TXD 0 R/W Selects the function of pin P22/TXD. 0: General I/O port 1: TXD output pin 0 TMOW 0 R/W Selects the function of pin P10/TMOW. 0: General I/O port 1: TMOW output pin
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Section 9 I/O Ports
9.1.2
Port Control Register 1 (PCR1)
PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR17 PCR16 PCR15 PCR14 PCR12 PCR11 PCR10 Initial Value 0 0 0 0 0 0 0 R/W W W W W W W W Description When the corresponding pin is designated in PMR1 as a general I/O pin, setting a PCR1 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Bit 3 is a reserved bit.
9.1.3
Port Data Register 1 (PDR1)
PDR1 is a general I/O port data register of port 1.
Bit 7 6 5 4 3 2 1 0 Bit Name P17 P16 P15 P14 P12 P11 P10 Initial Value 0 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description PDR1 stores output data for port 1 pins. If PDR1 is read while PCR1 bits are set to 1, the values stored in PDR1 are read. If PDR1 is read while PCR1 bits are cleared to 0, the pin states are read regardless of the value stored in PDR1. Bit 3 is a reserved bit. This bit is always read as 1.
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Section 9 I/O Ports
9.1.4
Port Pull-Up Control Register 1 (PUCR1)
PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports.
Bit 7 6 5 4 3 2 1 0 Bit Name PUCR17 PUCR16 PUCR15 PUCR14 PUCR12 PUCR11 PUCR10 Initial Value 0 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Only bits for which PCR1 is cleared are valid. The pullup MOSs of P17 to P14 and P12 to P10 pins enter the on-state when these bits are set to 1, while they enter the off-state when these bits are cleared to 0. Bit 3 is a reserved bit. This bit is always read as 1.
9.1.5
Pin Functions
The correspondence between the register specification and the port functions is shown below. * P17/IRQ3/TRGV pin
Register Bit Name Setting value PMR1 IRQ3 0 PCR1 PCR17 0 1 1 [Legend] X: Don't care. X Pin Function P17 input pin P17 output pin IRQ3 input/TRGV input pin
* P16/IRQ2 pin
Register Bit Name Setting value PMR1 IRQ2 0 PCR1 PCR16 0 1 1 [Legend] X: Don't care. X Pin Function P16 input pin P16 output pin IRQ2 input pin
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Section 9 I/O Ports
* P15/IRQ1/TMIB1 pin
Register Bit Name Setting value PMR1 IRQ1 0 PCR1 PCR15 0 1 1 [Legend] X: Don't care. X Pin Function P15 input pin P15 output pin IRQ1 input/TMIB1 input pin
* P14/IRQ0 pin
Register Bit Name Setting value PMR1 IRQ0 0 PCR1 PCR14 0 1 1 [Legend] X: Don't care. X Pin Function P14 input pin P14 output pin IRQ0 input pin
* P12 pin
Register Bit Name Setting value PCR1 PCR12 0 1 Pin Function P12 input pin P12 output pin
* P11/PWM pin
Register Bit Name Setting value PMR1 PWM 0 PCR1 PCR11 0 1 1 [Legend] X: Don't care. X Pin Function P11 input pin P11 output pin PWM output pin
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Section 9 I/O Ports
* P10/TMOW pin
Register Bit Name Setting value PMR1 TMOW 0 PCR1 PCR10 0 1 1 [Legend] X: Don't care. X Pin Function P10 input pin P10 output pin TMOW output pin
9.2
Port 2
Port 2 is a general I/O port also functioning as SCI3 I/O pins. Each pin of the port 2 is shown in figure 9.2. The register settings of PMR1 and SCI3 have priority for functions of the pins for both uses.
P24 P23 Port 2 P22/TXD P21/RXD P20/SCK3
Figure 9.2 Port 2 Pin Configuration Port 2 has the following registers. * Port control register 2 (PCR2) * Port data register 2 (PDR2) * Port mode register 3 (PMR3)
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Section 9 I/O Ports
9.2.1
Port Control Register 2 (PCR2)
PCR2 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 2.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR24 PCR23 PCR22 PCR21 PCR20 Initial Value 0 0 0 0 0 R/W W W W W W When each of the port 2 pins P24 to P20 functions as a general I/O port, setting a PCR2 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Description Reserved
9.2.2
Port Data Register 2 (PDR2)
PDR2 is a general I/O port data register of port 2.
Bit 7 6 5 4 3 2 1 0 Bit Name P24 P23 P22 P21 P20 Initial Value 1 1 1 0 0 0 0 0 R/W R/W R/W R/W R/W R/W PDR2 stores output data for port 2 pins. If PDR2 is read while PCR2 bits are set to 1, the values stored in PDR2 are read. If PDR2 is read while PCR2 bits are cleared to 0, the pin states are read regardless of the value stored in PDR2. Description Reserved These bits are always read as 1.
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Section 9 I/O Ports
9.2.3
Port Mode Register 3 (PMR3)
PMR3 selects the CMOS output or NMOS open-drain output for port 2.
Bit 7 6 5 4 3 Bit Name POF24 POF23 Initial Value 0 0 0 0 0 R/W R/W R/W When the bit is set to 1, the corresponding pin is cut off by PMOS and it functions as the NMOS open-drain output. When cleared to 0, the pin functions as the CMOS output. Reserved These bits are always read as 1. Description Reserved These bits are always read as 0.
2 1 0

1 1 1

9.2.4
Pin Functions
The correspondence between the register specification and the port functions is shown below. * P24 pin
Register Bit Name Setting Value PCR2 PCR24 0 1 Pin Function P24 input pin P24 output pin
* P23 pin
Register Bit Name Setting Value PCR2 PCR23 0 1 Pin Function P23 input pin P23 output pin
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Section 9 I/O Ports
* P22/TXD pin
Register Bit Name Setting Value PMR1 TXD 0 PCR2 PCR22 0 1 1 [Legend] X: Don't care. X Pin Function P22 input pin P22 output pin TXD output pin
* P21/RXD pin
Register Bit Name Setting Value SCR3 RE 0 PCR2 PCR21 0 1 1 [Legend] X: Don't care. X Pin Function P21 input pin P21 output pin RXD input pin
* P20/SCK3 pin
Register Bit Name Setting Value CKE1 0 SCR3 CKE0 0 SMR COM 0 PCR2 PCR20 0 1 0 0 1 [Legend] X: Don't care. 0 1 X 1 X X X X X Pin Function P20 input pin P20 output pin SCK3 output pin SCK3 output pin SCK3 input pin
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Section 9 I/O Ports
9.3
Port 3
Port 3 is a general I/O port. Each pin of the port 3 is shown in figure 9.3.
P37 P36 P35 P34 Port 3 P33 P32 P31 P30
Figure 9.3 Port 3 Pin Configuration Port 3 has the following registers. * Port control register 3 (PCR3) * Port data register 3 (PDR3) 9.3.1 Port Control Register 3 (PCR3)
PCR3 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 3.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR37 PCR36 PCR35 PCR34 PCR33 PCR32 PCR31 PCR30 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Setting a PCR3 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
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Section 9 I/O Ports
9.3.2
Port Data Register 3 (PDR3)
PDR3 is a general I/O port data register of port 3.
Bit 7 6 5 4 3 2 1 0 Bit Name P37 P36 P35 P34 P33 P32 P31 P30 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PDR3 stores output data for port 3 pins. If PDR3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read. If PDR3 is read while PCR3 bits are cleared to 0, the pin states are read regardless of the value stored in PDR3.
9.3.3
Pin Functions
The correspondence between the register specification and the port functions is shown below. * P37 pin
Register Bit Name Setting Value PCR3 PCR37 0 1 Pin Function P37 input pin P37 output pin
* P36 pin
Register Bit Name Setting Value PCR3 PCR36 0 1 Pin Function P36 input pin P36 output pin
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* P35 pin
Register Bit Name Setting Value PCR3 PCR35 0 1 Pin Function P35 input pin P35 output pin
* P34 pin
Register Bit Name PCR3 PCR34 Pin Function P34 input pin P34 output pin
Setting Value 0 1
* P33 pin
Register Bit Name PCR3 PCR33 Pin Function P33 input pin P33 output pin
Setting Value 0 1
* P32 pin
Register Bit Name PCR3 PCR32 Pin Function P32 input pin P32 output pin
Setting Value 0 1
* P31 pin
Register Bit Name PCR3 PCR31 Pin Function P31 input pin P31 output pin
Setting Value 0 1
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Section 9 I/O Ports
* P30 pin
Register Bit Name PCR3 PCR30 Pin Function P30 input pin P30 output pin
Setting Value 0 1
9.4
Port 5
Port 5 is a general I/O port also functioning as an I2C bus interface I/O pin, an A/D trigger input pin, and a wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.4. The register setting of the I2C bus interface has priority for functions of the pins P57/SCL and P56/SDA. Since the output buffer for pins P56 and P57 has the NMOS push-pull structure, it differs from an output buffer with the CMOS structure in the high-level output characteristics (see section 23, Electrical Characteristics).
P57/SCL P56/SDA P55/WKP5/ADTRG
Port 5
P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0
Figure 9.4 Port 5 Pin Configuration Port 5 has the following registers. * * * * Port mode register 5 (PMR5) Port control register 5 (PCR5) Port data register 5 (PDR5) Port pull-up control register 5 (PUCR5)
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Section 9 I/O Ports
9.4.1
Port Mode Register 5 (PMR5)
PMR5 switches the functions of pins in port 5.
Bit 7 6 Bit Name POF57 POF56 Initial Value 0 0 R/W R/W R/W Description When the bit is set to 1, the corresponding pin is cut off by PMOS and it functions as the NMOS open-drain output. When cleared to 0, the pin functions as the CMOS output. Selects the function of pin P55/WKP5/ADTRG. 0: General I/O port 1: WKP5/ADTRG input pin 4 WKP4 0 R/W Selects the function of pin P54/WKP4. 0: General I/O port 1: WKP4 input pin 3 WKP3 0 R/W Selects the function of pin P53/WKP3. 0: General I/O port 1: WKP3 input pin 2 WKP2 0 R/W Selects the function of pin P52/WKP2. 0: General I/O port 1: WKP2 input pin 1 WKP1 0 R/W Selects the function of pin P51/WKP1. 0: General I/O port 1: WKP1 input pin 0 WKP0 0 R/W Selects the function of pin P50/WKP0. 0: General I/O port 1: WKP0 input pin
5
WKP5
0
R/W
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Section 9 I/O Ports
9.4.2
Port Control Register 5 (PCR5)
PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR57 PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When each of the port 5 pins P57 to P50 functions as a general I/O port, setting a PCR5 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
9.4.3
Port Data Register 5 (PDR5)
PDR5 is a general I/O port data register of port 5.
Bit 7 6 5 4 3 2 1 0 Bit Name P57 P56 P55 P54 P53 P52 P51 P50 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PDR5 stores output data for port 5 pins. If PDR5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read. If PDR5 is read while PCR5 bits are cleared to 0, the pin states are read regardless of the value stored in PDR5.
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Section 9 I/O Ports
9.4.4
Port Pull-Up Control Register 5 (PUCR5)
PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports.
Bit 7 6 5 4 3 2 1 0 Bit Name PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Description Reserved These bits are always read as 0. Only bits for which PCR5 is cleared are valid. The pullup MOSs of the corresponding pins enter the on-state when these bits are set to 1, while they enter the offstate when these bits are cleared to 0.
9.4.5
Pin Functions
The correspondence between the register specification and the port functions is shown below. * P57/SCL pin
Register Bit Name Setting Value ICCR ICE 0 PCR5 PCR57 0 1 1 [Legend] X: Don't care. X Pin Function P57 input pin P57 output pin SCL I/O pin
SCL performs the NMOS open-drain output, that enables a direct bus drive.
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Section 9 I/O Ports
* P56/SDA pin
Register Bit Name Setting Value ICCR ICE 0 PCR5 PCR56 0 1 1 [Legend] X: Don't care. X Pin Function P56 input pin P56 output pin SDA I/O pin
SDA performs the NMOS open-drain output, that enables a direct bus drive. * P55/WKP5/ADTRG pin
Register Bit Name Setting Value PMR5 WKP5 0 PCR5 PCR55 0 1 1 [Legend] X: Don't care. X Pin Function P55 input pin P55 output pin WKP5/ADTRG input pin
* P54/WKP4 pin
Register Bit Name Setting Value PMR5 WKP4 0 PCR5 PCR54 0 1 1 [Legend] X: Don't care. X Pin Function P54 input pin P54 output pin WKP4 input pin
* P53/WKP3 pin
Register Bit Name Setting Value PMR5 WKP3 0 PCR5 PCR53 0 1 1 [Legend] X: Don't care. X Pin Function P53 input pin P53 output pin WKP3 input pin
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Section 9 I/O Ports
* P52/WKP2 pin
Register Bit Name Setting Value PMR5 WKP2 0 PCR5 PCR52 0 1 1 [Legend] X: Don't care. X Pin Function P52 input pin P52 output pin WKP2 input pin
* P51/WKP1 pin
Register Bit Name Setting Value PMR5 WKP1 0 PCR5 PCR51 0 1 1 [Legend] X: Don't care. X Pin Function P51 input pin P51 output pin WKP1 input pin
* P50/WKP0 pin
Register Bit Name Setting Value PMR5 WKP0 0 PCR5 PCR50 0 1 1 [Legend] X: Don't care. X Pin Function P50 input pin P50 output pin WKP0 input pin
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Section 9 I/O Ports
9.5
Port 6
Port 6 is a general I/O port also functioning as a timer Z I/O pin. Each pin of the port 6 is shown in figure 9.5. The register setting of the timer Z has priority for functions of the pins for both uses.
P67/FTIOD1 P66/FTIOC1 P65/FTIOB1 P64/FTIOA1 Port 6 P63/FTIOD0 P62/FTIOC0 P61/FTIOB0 P60/FTIOA0
Figure 9.5 Port 6 Pin Configuration Port 6 has the following registers. * Port control register 6 (PCR6) * Port data register 6 (PDR6) 9.5.1 Port Control Register 6 (PCR6)
PCR6 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 6.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR67 PCR66 PCR65 PCR64 PCR63 PCR62 PCR61 PCR60 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When each of the port 6 pins P67 to P60 functions as a general I/O port, setting a PCR6 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
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Section 9 I/O Ports
9.5.2
Port Data Register 6 (PDR6)
PDR6 is a general I/O port data register of port 6.
Bit 7 6 5 4 3 2 1 0 Bit Name P67 P66 P65 P64 P63 P62 P61 P60 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PDR6 stores output data for port 6 pins. If PDR6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read. If PDR6 is read while PCR6 bits are cleared to 0, the pin states are read regardless of the value stored in PDR6.
9.5.3
Pin Functions
The correspondence between the register specification and the port functions is shown below. * P67/FTIOD1 pin
Register Bit Name Setting Value TOER ED1 1 TFCR CMD1, CMD0 00 TPMR PWMD1 0 TIORC1 IOD2 to IOD0 PCR6 PCR67 Pin Function P67 input/FTIOD1 input pin P67 output pin FTIOD1 output pin
000 or 1XX 0 1
0
00
0 1
001 or 01X X XXX XXX
Other than X 00 [Legend] X: Don't care.
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Section 9 I/O Ports
* P66/FTIOC1 pin
Register Bit Name Setting Value TOER EC1 1 TFCR CMD1, CMD0 00 TPMR PWMC1 0 TIORC1 IOC2 to IOC0 PCR6 PCR66 Pin Function P66 input/FTIOC1 input pin P66 output pin FTIOC1 output pin
000 or 1XX 0 1
0
00
0 1
001 or 01X XXX XXX
X
Other than X 00 [Legend] X: Don't care.
* P65/FTIOB1 pin
Register Bit Name Setting Value TOER EB1 1 TFCR CMD1, CMD0 00 TPMR PWMB1 0 TIORA1 IOB2 to IOB0 000 or 1XX PCR6 PCR65 0 1 0 00 0 1 Other than X 00 [Legend] X: Don't care. 001 or 01X XXX XXX X Pin Function P65 input/FTIOB1 input pin P65 output pin FTIOB1 output pin
* P64/FTIOA1 pin
Register Bit Name Setting Value TOER EA1 1 TFCR TIORA1 PCR6 Pin Function P64 input/FTIOA1 input pin P64 output pin FTIOA1 output pin CMD1, CMD0 IOA2 to IOA0 PCR64 XX 000 or 1XX 0 1 0 [Legend] X: Don't care. 00 001 or 01X X
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Section 9 I/O Ports
* P63/FTIOD0 pin
Register Bit Name Setting Value TOER ED0 1 TFCR CMD1, CMD0 00 TPMR PWMD0 0 TIORC0 IOD2 to IOD0 000 or 1XX PCR6 PCR63 0 1 0 00 0 1 Other than X 00 [Legend] X: Don't care. 001 or 01X XXX XXX X Pin Function P63 input/FTIOD0 input pin P63 output pin FTIOD0 output pin
* P62/FTIOC0 pin
Register Bit Name Setting Value TOER EC0 1 TFCR CMD1, CMD0 00 TPMR PWMC0 0 TIORC0 IOC2 to IOC0 000 or 1XX PCR6 PCR62 0 1 0 00 0 1 Other than X 00 [Legend] X: Don't care. 001 or 01X XXX XXX X Pin Function P62 input/FTIOC0 input pin P62 output pin FTIOC0 output pin
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Section 9 I/O Ports
* P61/FTIOB0 pin
Register Bit Name Setting Value TOER EB0 1 TFCR CMD1, CMD0 00 TPMR PWMB0 0 TIORA0 IOB2 to IOB0 000 or 1XX PCR6 PCR61 0 1 0 00 0 1 Other than X 00 [Legend] X: Don't care. 001 or 01X XXX XXX X Pin Function P61 input/FTIOB0 input pin P61 output pin FTIOB0 output pin
* P60/FTIOA0 pin
Register Bit Name Setting Value 0 [Legend] X: Don't care. 00 0 TOER EA0 1 TFCR CMD1, CMD0 XX TFCR STCLK X TIORA0 IOA2 to IOA0 000 or 1XX 001 or 01X PCR6 PCR60 0 1 X Pin Function P60 input/FTIOA0 input pin P60 output pin FTIOA0 output pin
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Section 9 I/O Ports
9.6
Port 7
Port 7 is a general I/O port also functioning as a timer V I/O pin and SCI3_2 I/O pin. Each pin of the port 7 is shown in figure 9.6. The register settings of the timer V and SCI3_2 have priority for functions of the pins for both uses.
P77 P76/TMOV P75/TMCIV Port 7 P74/TMRIV P72/TXD_2 P71/RXD_2 P70/SCK3_2
Figure 9.6 Port 7 Pin Configuration Port 7 has the following registers. * Port control register 7 (PCR7) * Port data register 7 (PDR7) 9.6.1 Port Control Register 7 (PCR7)
PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 7.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR77 PCR76 PCR75 PCR74 PCR72 PCR71 PCR70 Initial Value 0 0 0 0 0 0 0 R/W W W W W W W W Description When each of the port 7 pins P77 to P74 and P72 to P70 functions as a general I/O port, setting a PCR7 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Bit 3 is a reserved bit.
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Section 9 I/O Ports
9.6.2
Port Data Register 7 (PDR7)
PDR7 is a general I/O port data register of port 7.
Bit 7 6 5 4 3 2 1 0 Bit Name P77 P76 P75 P74 P72 P71 P70 Initial Value 0 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description PDR7 stores output data for port 7 pins. If PDR7 is read while PCR7 bits are set to 1, the values stored in PDR7 are read. If PDR7 is read while PCR7 bits are cleared to 0, the pin states are read regardless of the value stored in PDR7. Bit 3 is a reserved bit. This bit is always read as 1.
9.6.3
Pin Functions
The correspondence between the register specification and the port functions is shown below. * P77 pin
Register Bit Name Setting Value PCR7 PCR77 0 1 Pin Function P77 input pin P77 output pin
* P76/TMOV pin
Register Bit Name Setting Value TCSRV PCR7 Pin Function P76 input pin P76 output pin TMOV output pin OS3 to OS0 PCR76 0000 0 1 Other than above [Legend] X: Don't care. X
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Section 9 I/O Ports
* P75/TMCIV pin
Register Bit Name Setting Value PCR7 PCR75 0 1 Pin Function P75 input/TMCIV input pin P75 output/TMCIV input pin
* P74/TMRIV pin
Register Bit Name Setting Value PCR7 PCR74 0 1 Pin Function P74 input/TMRIV input pin P74 output/TMRIV input pin
* P72/TXD_2 pin
Register Bit Name Setting Value PMR1 TXD2 0 PCR7 PCR72 0 1 1 [Legend] X: Don't care. X Pin Function P72 input pin P72 output pin TXD_2 output pin
* P71/RXD_2 pin
Register Bit Name Setting Value SCR3_2 RE 0 PCR7 PCR71 0 1 1 [Legend] X: Don't care. X Pin Function P71 input pin P71 output pin RXD_2 input pin
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Section 9 I/O Ports
* P70/SCK3_2 pin
Register Bit Name Setting Value CKE1 0 SCR3_2 CKE0 0 SMR_2 COM 0 PCR7 PCR70 0 1 0 0 1 [Legend] X: Don't care. 0 1 X 1 X X X X X Pin Function P70 input pin P70 output pin SCK3_2 output pin SCK3_2 output pin SCK3_2 input pin
9.7
Port 8
Port 8 is a general I/O port also functioning as a timer W I/O pin. Each pin of the port 8 is shown in figure 9.7. The register setting of the timer W has priority for functions of the pins P84/FTIOD, P83/FTIOC, P82/FTIOB, and P81/FTIOA. The P80/FTCI pin also functions as a timer W input port that is connected to the timer W regardless of the register setting of port 8.
P87 P86 P85 P84/FTIOD Port 8 P83/FTIOC P82/FTIOB P81/FTIOA P80/FTCI
Figure 9.7 Port 8 Pin Configuration Port 8 has the following registers. * Port control register 8 (PCR8) * Port data register 8 (PDR8)
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Section 9 I/O Ports
9.7.1
Port Control Register 8 (PCR8)
PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR87 PCR86 PCR85 PCR84 PCR83 PCR82 PCR81 PCR80 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When each of the port 8 pins P87 to P80 functions as a general I/O port, setting a PCR8 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
9.7.2
Port Data Register 8 (PDR8)
PDR8 is a general I/O port data register of port 8.
Bit 7 6 5 4 3 2 1 0 Bit Name P87 P86 P85 P84 P83 P82 P81 P80 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PDR8 stores output data for port 8 pins. If PDR8 is read while PCR8 bits are set to 1, the values stored in PDR8 are read. If PDR8 is read while PCR8 bits are cleared to 0, the pin states are read regardless of the value stored in PDR8.
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Section 9 I/O Ports
9.7.3
Pin Functions
The correspondence between the register specification and the port functions is shown below. * P87 pin
Register Bit Name Setting Value PCR8 PCR87 0 1 Pin Function P87 input pin P87 output pin
* P86 pin
Register Bit Name Setting Value PCR8 PCR86 0 1 Pin Function P86 input pin P86 output pin
* P85 pin
Register Bit Name Setting Value PCR8 PCR85 0 1 Pin Function P85 input pin P85 output pin
* P84/FTIOD pin
Register Bit Name Setting Value TMRW PWMD 0 IOD2 0 TIOR1 IOD1 0 IOD0 0 PCR8 PCR84 0 1 0 0 1 0 1 X 1 X X X X 0 1 1 [Legend] X: Don't care. X X X X Pin Function P84 input/FTIOD input pin P84 output/FTIOD input pin FTIOD output pin FTIOD output pin P84 input/FTIOD input pin P84 output/FTIOD input pin PWM output
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Section 9 I/O Ports
* P83/FTIOC pin
Register Bit Name Setting Value TMRW PWMC 0 IOC2 0 TIOR1 IOC1 0 IOC0 0 PCR8 PCR83 0 1 0 0 1 0 1 X 1 X X X X 0 1 1 [Legend] X: Don't care. X X X X Pin Function P83 input/FTIOC input pin P83 output/FTIOC input pin FTIOC output pin FTIOC output pin P83 input/FTIOC input pin P83 output/FTIOC input pin PWM output
* P82/FTIOB pin
Register Bit Name Setting Value TMRW PWMB 0 IOB2 0 TIOR0 IOB1 0 IOB0 0 PCR8 PCR82 0 1 0 0 1 0 1 X 1 X X X X 0 1 1 [Legend] X: Don't care. X X X X Pin Function P82 input/FTIOB input pin P82 output/FTIOB input pin FTIOB output pin FTIOB output pin P82 input/FTIOB input pin P82 output/FTIOB input pin PWM output
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Section 9 I/O Ports
* P81/FTIOA pin
Register Bit Name Setting Value IOA2 0 TIOR0 IOA1 0 IOA0 0 PCR8 PCR81 Pin Function 0 1 0 0 1 [Legend] X: Don't care. 0 1 X 1 X X X X 0 1 P81 input/FTIOA input pin P81 output/FTIOA input pin FTIOA output pin FTIOA output pin P81 input/FTIOA input pin P81 output/FTIOA input pin
* P80/FTCI pin
Register Bit Name Setting Value PCR8 PCR80 0 1 Pin Function P80 input/FTCI input pin P80 output/FTCI input pin
9.8
Port 9
Port 9 is a general I/O port also functioning as an SCI3_3 I/O pin. Each pin of the port 9 is shown in figure 9.8. The register setting of the SCI3_3 has priority for functions of the pins for both uses.
P97 P96 P95 P94 Port 9 P93 P92/TXD_3 P91/RXD_3 P90/SCK3_3
Figure 9.8 Port 9 Pin Configuration
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Section 9 I/O Ports
Port 9 has the following registers. * Port control register 9 (PCR9) * Port data register 9 (PDR9) 9.8.1 Port Control Register 9 (PCR9)
PCR9 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 9.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR97 PCR96 PCR95 PCR94 PCR93 PCR92 PCR91 PCR90 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When each of the port 9 pins P97 to P90 functions as a general I/O port, setting a PCR9 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
9.8.2
Port Data Register 9 (PDR9)
PDR9 is a general I/O port data register of port 9.
Bit 7 6 5 4 3 2 1 0 Bit Name P97 P96 P95 P94 P93 P92 P91 P90 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PDR9 stores output data for port 9 pins. If PDR9 is read while PCR9 bits are set to 1, the values stored in PDR9 are read. If PDR9 is read while PCR9 bits are cleared to 0, the pin states are read regardless of the value stored in PDR9.
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Section 9 I/O Ports
9.8.3
Pin Functions
The correspondence between the register specification and the port functions is shown below. * P97 pin
Register Bit Name Setting Value PCR9 PCR97 0 1 Pin Function P97 input pin P97 output pin
* P96 pin
Register Bit Name Setting Value PCR9 PCR96 0 1 Pin Function P96 input pin P96 output pin
* P95 pin
Register Bit Name Setting Value PCR9 PCR95 0 1 Pin Function P95 input pin P95 output pin
* P94 pin
Register Bit Name Setting Value PCR9 PCR94 0 1 Pin Function P94 input pin P94 output pin
* P93 pin
Register Bit Name Setting Value PCR9 PCR93 0 1 Pin Function P93 input pin P93 output pin
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Section 9 I/O Ports
* P92/TXD_3 pin
Register Bit Name Setting Value SMCR3 TXD_3 0 PCR9 PCR92 0 1 1 [Legend] X: Don't care. X Pin Function P92 input pin P92 output pin TXD_3 output pin
* P91/RXD_3 pin
Register Bit Name Setting Value SCR3_3 RE 0 PCR9 PCR91 0 1 1 [Legend] X: Don't care. X Pin Function P91 input pin P91 output pin RXD_3 input pin
* P90/SCK3_3 pin
Register Bit Name Setting Value CKE1 0 SCR3_3 CKE0 0 SMR3_3 COM 0 PCR9 PCR90 0 1 0 0 1 [Legend] X: Don't care. 0 1 X 1 X X X X X Pin Function P90 input pin P90 output pin SCK3_3 output pin SCK3_3 output pin SCK3_3 input pin
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Section 9 I/O Ports
9.9
Port B
Port B is an input port also functioning as an A/D converter analog input pin. Each pin of the port B is shown in figure 9.9.
PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 Port B PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0
Figure 9.9 Port B Pin Configuration Port B has the following register. * Port data register B (PDRB) 9.9.1 Port Data Register B (PDRB)
PDRB is a general input-only port data register of port B.
Bit 7 6 5 4 3 2 1 0 Bit Name PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Initial Value R/W R R R R R R R R Description The input value of each pin is read by reading this register. However, if a port B pin is designated as an analog input channel by ADCSR of A/D converter, 0 is read.
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Section 9 I/O Ports
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Section 10 Realtime Clock (RTC)
Section 10 Realtime Clock (RTC)
The realtime clock (RTC) is a timer used to count time ranging from a second to a week. Figure 10.1 shows the block diagram of the RTC.
10.1
* * * * * * *
Features
Counts seconds, minutes, hours, and day-of-week Start/stop function Reset function Readable/writable counter of seconds, minutes, hours, and day-of-week with BCD codes Periodic (seconds, minutes, hours, days, and weeks) interrupts 8-bit free running counter Selection of clock source
PSS 32-kHz oscillator circuit
RTCCSR
1/4
RSECDR
RHRDR TMOW Clock count control circuit
RWKDR
RTCCR1
RTCCR2
Interrupt control circuit [Legend] RTCCSR: Clock source select register RSECDR: Second date register/free running counter data register RMINDR: Minute date register RHRDR: Hour date register RWKDR: Day-of-week date register RTCCR1: RTC control register 1 RTCCR2: RTC control register 2 Prescaler S PSS:
Figure 10.1 Block Diagram of RTC
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Internal data bus
Interrupt
RMINDR
Section 10 Realtime Clock (RTC)
10.2
Input/Output Pin
Table 10.1 shows the RTC input/output pin. Table 10.1 Pin Configuration
Name Clock output Abbreviation TMOW I/O Output Function RTC divided clock output
10.3
Register Descriptions
The RTC has the following registers. * * * * * * * Second data register/free running counter data register (RSECDR) Minute data register (RMINDR) Hour data register (RHRDR) Day-of-week data register (RWKDR) RTC control register 1 (RTCCR1) RTC control register 2 (RTCCR2) Clock source select register (RTCCSR)
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Section 10 Realtime Clock (RTC)
10.3.1
Second Data Register/Free Running Counter Data Register (RSECDR)
RSECDR counts the BCD-coded second value. The setting range is decimal 00 to 59. It is an 8-bit read register used as a counter, when it operates as a free running counter. For more information on reading seconds, minutes, hours, and day-of-week, see section 10.4.3, Data Reading Procedure.
Bit 7 Bit Name BSY Initial Value -- R/W R Description RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers. When this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 5 4 3 2 1 0 SC12 SC11 SC10 SC03 SC02 SC01 SC00 -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W Counting One's Position of Seconds Counts on 0 to 9 once per second. When a carry is generated, 1 is added to the ten's position. Counting Ten's Position of Seconds Counts on 0 to 5 for 60-second counting.
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Section 10 Realtime Clock (RTC)
10.3.2
Minute Data Register (RMINDR)
RMINDR counts the BCD-coded minute value on the carry generated once per minute by the RSECDR counting. The setting range is decimal 00 to 59.
Bit 7 Bit Name BSY Initial Value -- R/W R Description RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers. When this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 5 4 3 2 1 0 MN12 MN11 MN10 MN03 MN02 MN01 MN00 -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W Counting One's Position of Minutes Counts on 0 to 9 once per minute. When a carry is generated, 1 is added to the ten's position. Counting Ten's Position of Minutes Counts on 0 to 5 for 60-minute counting.
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Section 10 Realtime Clock (RTC)
10.3.3
Hour Data Register (RHRDR)
RHRDR counts the BCD-coded hour value on the carry generated once per hour by RMINDR. The setting range is either decimal 00 to 11 or 00 to 23 by the selection of the 12/24 bit in RTCCR1.
Bit 7 Bit Name BSY Initial Value -- R/W R Description RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers. When this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 5 4 3 2 1 0 -- HR11 HR10 HR03 HR02 HR01 HR00 0 -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W Reserved This bit is always read as 0. Counting Ten's Position of Hours Counts on 0 to 2 for ten's position of hours. Counting One's Position of Hours Counts on 0 to 9 once per hour. When a carry is generated, 1 is added to the ten's position.
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Section 10 Realtime Clock (RTC)
10.3.4
Day-of-Week Data Register (RWKDR)
RWKDR counts the BCD-coded day-of-week value on the carry generated once per day by RHRDR. The setting range is decimal 0 to 6 using bits WK2 to WK0.
Bit 7 Bit Name BSY Initial Value -- R/W R Description RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers. When this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 5 4 3 2 1 0 -- -- -- -- WK2 WK1 WK0 0 0 0 0 -- -- -- -- -- -- -- R/W R/W R/W Day-of-Week Counting Day-of-week is indicated with a binary code 000: Sunday 001: Monday 010: Tuesday 011: Wednesday 100: Thursday 101: Friday 110: Saturday 111: Reserved (setting prohibited) Reserved These bits are always read as 0.
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Section 10 Realtime Clock (RTC)
10.3.5
RTC Control Register 1 (RTCCR1)
RTCCR1 controls start/stop and reset of the clock timer. For the definition of time expression, see figure 10.2.
Bit 7 Bit Name RUN Initial Value -- R/W R/W Description RTC Operation Start 0: Stops RTC operation 1: Starts RTC operation Operating Mode 0: RTC operates in 12-hour mode. RHRDR counts on 0 to 11. 1: RTC operates in 24-hour mode. RHRDR counts on 0 to 23. a.m./p.m. 0: Indicates a.m. when RTC is in the 12-hour mode. 1: Indicates p.m. when RTC is in the 12-hour mode. Reset 0: Normal operation 1: Resets registers and control circuits except RTCCSR and this bit. Clear this bit to 0 after having been set to 1. Interrupt Generation Timing 0: Generates a second, minute, hour, or day-of-week periodic interrupt during RTC busy period. 1: Generates a second, minute, hour, or day-of-week periodic interrupt immediately after completing RTC busy period. Reserved These bits are always read as 0.
6
12/24
--
R/W
5
PM
--
R/W
4
RST
0
R/W
3
INT
--
R/W
2 1 0
-- -- --
0 0 0
-- -- --
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Section 10 Realtime Clock (RTC)
Noon 24-hour count 0 12-hour count 0 PM 1 1 2 2 3 3 4 4 567 567 0 (Morning) 8 8 9 10 11 12 13 14 15 16 17 9 10 11 0 1 2 3 4 5 1 (Afternoon)
24-hour count 18 19 20 21 22 23 0 12-hour count 6 7 8 9 10 11 0 1 (Afternoon) 0 PM
Figure 10.2 Definition of Time Expression
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Section 10 Realtime Clock (RTC)
10.3.6
RTC Control Register 2 (RTCCR2)
RTCCR2 controls RTC periodic interrupts of weeks, days, hours, minutes, and seconds. Enabling interrupts of weeks, days, hours, minutes, and seconds sets the IRRTA flag to 1 in the interrupt flag register 1 (IRR1) when an interrupt occurs. It also controls an overflow interrupt of a free running counter when RTC operates as a free running counter.
Bit 7 6 5 Bit Name -- -- FOIE Initial Value 0 0 -- R/W -- -- R/W Description Reserved These bits are always read as 0. Free Running Counter Overflow Interrupt Enable 0: Disables an overflow interrupt 1: Enables an overflow interrupt 4 WKIE -- R/W Week Periodic Interrupt Enable 0: Disables a week periodic interrupt 1: Enables a week periodic interrupt 3 DYIE -- R/W Day Periodic Interrupt Enable 0: Disables a day periodic interrupt 1: Enables a day periodic interrupt 2 HRIE -- R/W Hour Periodic Interrupt Enable 0: Disables an hour periodic interrupt 1: Enables an hour periodic interrupt 1 MNIE -- R/W Minute Periodic Interrupt Enable 0: Disables a minute periodic interrupt 1: Enables a minute periodic interrupt 0 SEIE -- R/W Second Periodic Interrupt Enable 0: Disables a second periodic interrupt 1: Enables a second periodic interrupt
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Section 10 Realtime Clock (RTC)
10.3.7
Clock Source Select Register (RTCCSR)
RTCCSR selects clock source. A free running counter controls start/stop of counter operation by the RUN bit in RTCCR1. When a clock other than 32.768 kHz is selected, the RTC is disabled and operates as an 8-bit free running counter. When the RTC operates as an 8-bit free running counter, RSECDR enables counter values to be read. An interrupt can be generated by setting 1 to the FOIE bit in RTCCR2 and enabling an overflow interrupt of the free running counter. A clock in which the system clock is divided by 32, 16, 8, or 4 is output in active or sleep mode.
Bit 7 6 5 Bit Name -- RCS6 RCS5 Initial Value 0 0 0 R/W -- R/W R/W Description Reserved This bit is always read as 0. Clock Output Selection Selects a clock output from the TMOW pin when setting TMOW in PMR1 to 1. 00: /4 01: /8 10: /16 11: /32 4 3 2 1 0 -- RCS3 RCS2 RCS1 RCS0 0 1 0 0 0 -- R/W R/W R/W R/W Reserved This bit is always read as 0. Clock Source Selection 0000: /8 Free running counter operation 0001: /32 Free running counter operation 0010: /128 Free running counter operation 0011: /256 Free running counter operation 0100: /512 Free running counter operation 0101: /2048 Free running counter operation 0110: /4096 Free running counter operation 0111: /8192 Free running counter operation 1XXX: 32.768 kHzRTC operation [Legend] X: Don't care
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Section 10 Realtime Clock (RTC)
10.4
10.4.1
Operation
Initial Settings of Registers after Power-On
The RTC registers that store second, minute, hour, and day-of week data are not reset by a RES input. Therefore, all registers must be set to their initial values after power-on. Once the register setting are made, the RTC provides an accurate time as long as power is supplied regardless of a RES input. 10.4.2 Initial Setting Procedure
Figure 10.3 shows the procedure for the initial setting of the RTC. To set the RTC again, also follow this procedure.
RUN in RTCCR1=0 RST in RTCCR1=1 RST in RTCCR1=0 Set RTCCSR, RSECDR, RMINDR,RHRDR, RWKDR,12/24 in RTCCR1, and PM RUN in RTCCR1=1
RTC operation is stopped.
RTC registers and clock count controller are reset.
Clock output and clock source are selected and second, minute, hour, day-of-week,operating mode, and a.m/p.m are set. RTC operation is started.
Figure 10.3 Initial Setting Procedure
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Section 10 Realtime Clock (RTC)
10.4.3
Data Reading Procedure
When the seconds, minutes, hours, or day-of-week datum is updated while time data is being read, the data obtained may not be correct, and so the time data must be read again. Figure 10.4 shows an example in which correct data is not obtained. In this example, since only RSECDR is read after data update, about 1-minute inconsistency occurs. To avoid reading in this timing, the following processing must be performed. 1. Check the setting of the BSY bit, and when the BSY bit changes from 1 to 0, read from the second, minute, hour, and day-of-week registers. When about 62.5 ms is passed after the BSY bit is set to 1, the registers are updated, and the BSY bit is cleared to 0. 2. Making use of interrupts, read from the second, minute, hour, and day-of week registers after the IRRTA flag in IRR1 is set to 1 and the BSY bit is confirmed to be 0. 3. Read from the second, minute, hour, and day-of week registers twice in a row, and if there is no change in the read data, the read data is used.
Before update BSY bit = 0 RWKDR = H'03, RHDDR = H'13, RMINDR = H'46, RSECDR = H'59
Processing flow
(1) Day-of-week data register read (2) Hour data register read (3) Minute data register read
H'03 H'13 H'46
BSY bit -> 1 (under data update) After update BSY bit -> 0 RWKDR = H'03, RHDDR = H'13, RMINDR = H'47, RSECDR = H'00
(4) Second data register read
H'00
Figure 10.4 Example: Reading of Inaccurate Time Data
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Section 10 Realtime Clock (RTC)
10.5
Interrupt Sources
There are five kinds of RTC interrupts: week interrupts, day interrupts, hour interrupts, minute interrupts, and second interrupts. When using an interrupt, initiate the RTC last after other registers are set. Do not set multiple interrupt enable bits in RTCCR2 simultaneously to 1. When an interrupt request of the RTC occurs, the IRRTA flag in IRR1 is set to 1. When clearing the flag, write 0. Table 10.2 Interrupt Sources
Interrupt Name Overflow interrupt Week periodic interrupt Day periodic interrupt Hour periodic interrupt Minute periodic interrupt Second periodic interrupt Interrupt Source Occurs when the free running counter is overflown. Occurs every week when the day-of-week date register value becomes 0. Interrupt Enable Bit FOIE WKIE
Occurs every day when the day-of-week date DYIE register is counted. Occurs every hour when the hour date register is counted. Occurs every minute when the minute date register is counted. Occurs every second when the second date register is counted. HRIE MNIE SCIE
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Section 10 Realtime Clock (RTC)
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Section 11 Timer B1
Section 11 Timer B1
Timer B1 is an 8-bit timer that increments each time a clock pulse is input. This timer has two operating modes, interval and auto reload. Figure 11.1 shows a block diagram of timer B1.
11.1
Features
* Selection of seven internal clock sources (/8192, /2048, /512, /256, /64, /16, and /4) or an external clock (can be used to count external events). * An interrupt is generated when the counter overflows.
TMB1
PSS TCB1
TMIB1 TLB1 [Legend] TMB1: TCB1: TLB1: IRRTB1: PSS: TMIB1: Timer mode register B1 Timer counter B1 Timer load register B1 Timer B1 interrupt request flag Prescaler S Timer B1 event input
IRRTB1
Figure 11.1 Block Diagram of Timer B1
11.2
Input/Output Pin
Table 11.1 shows the timer B1 pin configuration. Table 11.1 Pin Configuration
Name Timer B1 event input Abbreviation TMIB1 I/O Input Function Event input to TCB1
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Internal data bus
Section 11 Timer B1
11.3
Register Descriptions
The timer B1 has the following registers. * Timer mode register B1 (TMB1) * Timer counter B1 (TCB1) * Timer load register B1 (TLB1) 11.3.1 Timer Mode Register B1 (TMB1)
TMB1 selects the auto-reload function and input clock.
Bit 7 Bit Name TMB17 Initial Value 0 R/W R/W Description Auto-Reload Function Select 0: Interval timer function selected 1: Auto-reload function selected 6 5 4 3 2 1 0 TMB12 TMB11 TMB10 1 1 1 1 0 0 0 R/W R/W R/W Clock Select 000: Internal clock: /8192 001: Internal clock: /2048 010: Internal clock: /512 011: Internal clock: /256 100: Internal clock: /64 101: Internal clock: /16 110: Internal clock: /4 111: External event (TMIB1): rising or falling edge* Note: * The edge of the external event signal is selected by bit IEG1 in the interrupt edge select register 1 (IEGR1). See section 3.2.1, Interrupt Edge Select Register 1 (IEGR1), for details. Before setting TMB12 to TMB10 to 1, IRQ1 in the port mode register 1 (PMR1) should be set to 1. Reserved These bits are always read as 1.
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Section 11 Timer B1
11.3.2
Timer Counter B1 (TCB1)
TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMB12 to TMB10 in TMB1. TCB1 values can be read by the CPU at any time. When TCB1 overflows from H'FF to H'00 or to the value set in TLB1, the IRRTB1 flag in IRR2 is set to 1. TCB1 is allocated to the same address as TLB1. TCB1 is initialized to H'00. 11.3.3 Timer Load Register B1 (TLB1)
TLB1 is an 8-bit write-only register for setting the reload value of TCB1. When a reload value is set in TLB1, the same value is loaded into TCB1 as well, and TCB1 starts counting up from that value. When TCB1 overflows during operation in auto-reload mode, the TLB1 value is loaded into TCB1. Accordingly, overflow periods can be set within the range of 1 to 256 input clocks. TLB1 is allocated to the same address as TCB1. TLB1 is initialized to H'00.
11.4
11.4.1
Operation
Interval Timer Operation
When bit TMB17 in TMB1 is cleared to 0, timer B1 functions as an 8-bit interval timer. Upon reset, TCB1 is cleared to H'00 and bit TMB17 is cleared to 0, so up-counting and interval timing resume immediately. The operating clock of timer B1 is selected from seven internal clock signals output by prescaler S, or an external clock input at pin TMB1. The selection is made by bits TMB12 to TMB10 in TMB1. After the count value in TMB1 reaches H'FF, the next clock signal input causes timer B1 to overflow, setting flag IRRTB1 in IRR2 to 1. If IENTB1 in IENR2 is 1, an interrupt is requested to the CPU. At overflow, TCB1 returns to H'00 and starts counting up again. During interval timer operation (TMB17 = 0), when a value is set in TLB1, the same value is set in TCB1.
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Section 11 Timer B1
11.4.2
Auto-Reload Timer Operation
Setting bit TMB17 in TMB1 to 1 causes timer B1 to function as an 8-bit auto-reload timer. When a reload value is set in TLB1, the same value is loaded into TCB1, becoming the value from which TCB1 starts its count. After the count value in TCB1 reaches H'FF, the next clock signal input causes timer B1 to overflow. The TLB1 value is then loaded into TCB1, and the count continues from that value. The overflow period can be set within a range from 1 to 256 input clocks, depending on the TLB1 value. The clock sources and interrupts in auto-reload mode are the same as in interval mode. In autoreload mode (TMB17 = 1), when a new value is set in TLB1, the TLB1 value is also loaded into TCB1. 11.4.3 Event Counter Operation
Timer B1 can operate as an event counter in which TMIB1 is set to an event input pin. External event counting is selected by setting bits TMB12 to TMB10 in TMB1 to 1. TCB1 counts up at rising or falling edge of an external event signal input at pin TMB1. When timer B1 is used to count external event input, bit IRQ1 in PMR1 should be set to 1 and IEN1 in IENR1 should be cleared to 0 to disable IRQ1 interrupt requests.
11.5
Timer B1 Operating Modes
Table 11.2 shows the timer B1 operating modes. Table 11.2 Timer B1 Operating Modes
Operating Mode TCB1 Interval Auto-reload TMB1 Reset Reset Reset Reset Active Functions Functions Functions Sleep Functions Functions Retained Subactive Halted Halted Retained Subsleep Halted Halted Retained Standby Halted Halted Retained
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Section 12 Timer V
Section 12 Timer V
Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Comparematch signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at the TRGV pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. Figure 12.1 shows a block diagram of timer V.
12.1
Features
* Choice of seven clock signals is available. Choice of six internal clock sources (/128, /64, /32, /16, /8, /4) or an external clock. * Counter can be cleared by compare match A or B, or by an external reset signal. If the count stop function is selected, the counter can be halted when cleared. * Timer output is controlled by two independent compare match signals, enabling pulse output with an arbitrary duty cycle, PWM output, and other applications. * Three interrupt sources: compare match A, compare match B, timer overflow * Counting can be initiated by trigger input at the TRGV pin. The rising edge, falling edge, or both edges of the TRGV input can be selected.
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Section 12 Timer V
TCRV1 TCORB TRGV Trigger control Comparator TCNTV Comparator PSS TCORA TMRIV Clear control TCRV0 Interrupt request control TMOV Output control TCSRV
TMCIV
Clock select
[Legend] TCORA: Time constant register A TCORB: Time constant register B TCNTV: Timer counter V TCSRV: Timer control/status register V TCRV0: Timer control register V0
TCRV1: PSS: CMIA: CMIB: OVI:
Timer control register V1 Prescaler S Compare-match interrupt A Compare-match interrupt B Overflow interupt
CMIA CMIB OVI
Figure 12.1 Block Diagram of Timer V
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Internal data bus
Section 12 Timer V
12.2
Input/Output Pins
Table 12.1 shows the timer V pin configuration. Table 12.1 Pin Configuration
Name Timer V output Timer V clock input Timer V reset input Trigger input Abbreviation TMOV TMCIV TMRIV TRGV I/O Output Input Input Input Function Timer V waveform output Clock input to TCNTV External input to reset TCNTV Trigger input to initiate counting
12.3
Register Descriptions
Time V has the following registers. * * * * * * Timer counter V (TCNTV) Timer constant register A (TCORA) Timer constant register B (TCORB) Timer control register V0 (TCRV0) Timer control/status register V (TCSRV) Timer control register V1 (TCRV1) Timer Counter V (TCNTV)
12.3.1
TCNTV is an 8-bit up-counter. The clock source is selected by bits CKS2 to CKS0 in timer control register V0 (TCRV0). The TCNTV value can be read and written by the CPU at any time. TCNTV can be cleared by an external reset input signal, or by compare match A or B. The clearing signal is selected by bits CCLR1 and CCLR0 in TCRV0. When TCNTV overflows, OVF is set to 1 in timer control/status register V (TCSRV). TCNTV is initialized to H'00.
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Section 12 Timer V
12.3.2
Time Constant Registers A, B (TCORA, TCORB)
TCORA and TCORB have the same function. TCORA and TCORB are 8-bit readable/writable registers. TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match, CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested. Note that they must not be compared during the T3 state of a TCORA write cycle. Timer output from the TMOV pin can be controlled by the identifying signal (compare match A) and the settings of bits OS3 to OS0 in TCSRV. TCORA and TCORB are initialized to H'FF.
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Section 12 Timer V
12.3.3
Timer Control Register V0 (TCRV0)
TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV, and controls each interrupt request.
Bit 7 Bit Name CMIEB Initial Value 0 R/W R/W Description Compare Match Interrupt Enable B When this bit is set to 1, interrupt request from the CMFB bit in TCSRV is enabled. Compare Match Interrupt Enable A When this bit is set to 1, interrupt request from the CMFA bit in TCSRV is enabled. Timer Overflow Interrupt Enable When this bit is set to 1, interrupt request from the OVF bit in TCSRV is enabled. Counter Clear 1 and 0 These bits specify the clearing conditions of TCNTV. 00: Clearing is disabled 01: Cleared by compare match A 10: Cleared by compare match B 11: Cleared on the rising edge of the TMRIV pin. The operation of TCNTV after clearing depends on TRGE in TCRV1. Clock Select 2 to 0 These bits select clock signals to input to TCNTV and the counting condition in combination with ICKS0 in TCRV1. Refer to table 12.2.
6
CMIEA
0
R/W
5
OVIE
0
R/W
4 3
CCLR1 CCLR0
0 0
R/W R/W
2 1 0
CKS2 CKS1 CKS0
0 0 0
R/W R/W R/W
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Section 12 Timer V
Table 12.2 Clock Signals to Input to TCNTV and Counting Conditions
TCRV0 Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 TCRV1 Bit 0 ICKS0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 1 Description Clock input prohibited Internal clock: counts on /4, falling edge Internal clock: counts on /8, falling edge Internal clock: counts on /16, falling edge Internal clock: counts on /32, falling edge Internal clock: counts on /64, falling edge Internal clock: counts on /128, falling edge Clock input prohibited External clock: counts on rising edge External clock: counts on falling edge External clock: counts on rising and falling edge
12.3.4
Timer Control/Status Register V (TCSRV)
TCSRV indicates the status flag and controls outputs by using a compare match.
Bit 7 Bit Name CMFB Initial Value 0 R/W R/W Description Compare Match Flag B Setting condition: When the TCNTV value matches the TCORB value Clearing condition: After reading CMFB = 1, cleared by writing 0 to CMFB 6 CMFA 0 R/W Compare Match Flag A Setting condition: When the TCNTV value matches the TCORA value Clearing condition: After reading CMFA = 1, cleared by writing 0 to CMFA
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Section 12 Timer V
Bit 5
Bit Name OVF
Initial Value 0
R/W R/W
Description Timer Overflow Flag Setting condition: When TCNTV overflows from H'FF to H'00 Clearing condition: After reading OVF = 1, cleared by writing 0 to OVF
4 3 2
OS3 OS2
1 0 0
R/W R/W
Reserved This bit is always read as 1. Output Select 3 and 2 These bits select an output method for the TOMV pin by the compare match of TCORB and TCNTV. 00: No change 01: 0 output 10: 1 output 11: Output toggles
1 0
OS1 OS0
0 0
R/W R/W
Output Select 1 and 0 These bits select an output method for the TOMV pin by the compare match of TCORA and TCNTV. 00: No change 01: 0 output 10: 1 output 11: Output toggles
OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two output levels can be controlled independently. After a reset, the timer output is 0 until the first compare match.
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Section 12 Timer V
12.3.5
Timer Control Register V1 (TCRV1)
TCRV1 selects the edge at the TRGV pin, enables TRGV input, and selects the clock input to TCNTV.
Bit 7 to 5 4 3 Bit Name TVEG1 TVEG0 Initial Value All 1 0 0 R/W R/W R/W Description Reserved These bits are always read as 1. TRGV Input Edge Select These bits select the TRGV input edge. 00: TRGV trigger input is prohibited 01: Rising edge is selected 10: Falling edge is selected 11: Rising and falling edges are both selected 2 TRGE 0 R/W TCNT starts counting up by the input of the edge which is selected by TVEG1 and TVEG0. 0: Disables starting counting-up TCNTV by the input of the TRGV pin and halting counting-up TCNTV when TCNTV is cleared by a compare match. 1: Enables starting counting-up TCNTV by the input of the TRGV pin and halting counting-up TCNTV when TCNTV is cleared by a compare match. 1 0 ICKS0 1 0 R/W Reserved This bit is always read as 1. Internal Clock Select 0 This bit selects clock signals to input to TCNTV in combination with CKS2 to CKS0 in TCRV0. Refer to table 12.2.
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Section 12 Timer V
12.4
12.4.1
Operation
Timer V Operation
1. According to table 12.2, six internal/external clock signals output by prescaler S can be selected as the timer V operating clock signals. When the operating clock signal is selected, TCNTV starts counting-up. Figure 12.2 shows the count timing with an internal clock signal selected, and figure 12.3 shows the count timing with both edges of an external clock signal selected. 2. When TCNTV overflows (changes from H'FF to H'00), the overflow flag (OVF) in TCRV0 will be set. The timing at this time is shown in figure 12.4. An interrupt request is sent to the CPU when OVIE in TCRV0 is 1. 3. TCNTV is constantly compared with TCORA and TCORB. Compare match flag A or B (CMFA or CMFB) is set to 1 when TCNTV matches TCORA or TCORB, respectively. The compare-match signal is generated in the last state in which the values match. Figure 12.5 shows the timing. An interrupt request is generated for the CPU when CMIEA or CMIEB in TCRV0 is 1. 4. When a compare match A or B is generated, the TMOV responds with the output value selected by bits OS3 to OS0 in TCSRV. Figure 12.6 shows the timing when the output is toggled by compare match A. 5. When CCLR1 or CCLR0 in TCRV0 is 01 or 10, TCNTV can be cleared by the corresponding compare match. Figure 12.7 shows the timing. 6. When CCLR1 or CCLR0 in TCRV0 is 11, TCNTV can be cleared by the rising edge of the input of TMRIV pin. A TMRIV input pulse-width of at least 1.5 system clocks is necessary. Figure 12.8 shows the timing. 7. When a counter-clearing source is generated with TRGE in TCRV1 set to 1, the counting-up is halted as soon as TCNTV is cleared. TCNTV resumes counting-up when the edge selected by TVEG1 or TVEG0 in TCRV1 is input from the TGRV pin.
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Section 12 Timer V
Internal clock
TCNTV input clock
TCNTV
N-1
N
N+1
Figure 12.2 Increment Timing with Internal Clock
TMCIV (External clock input pin) TCNTV input clock
TCNTV
N-1
N
N+1
Figure 12.3 Increment Timing with External Clock
TCNTV
H'FF
H'00
Overflow signal
OVF
Figure 12.4 OVF Set Timing
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Section 12 Timer V
TCNTV
N
N+1
TCORA or TCORB Compare match signal CMFA or CMFB
N
Figure 12.5 CMFA and CMFB Set Timing
Compare match A signal
Timer V output pin
Figure 12.6 TMOV Output Timing
Compare match A signal
TCNTV
N
H'00
Figure 12.7 Clear Timing by Compare Match
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Section 12 Timer V
Compare match A signal Timer V output pin TCNTV N-1 N H'00
Figure 12.8 Clear Timing by TMRIV Input
12.5
12.5.1
Timer V Application Examples
Pulse Output with Arbitrary Duty Cycle
Figure 12.9 shows an example of output of pulses with an arbitrary duty cycle. 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORA. 2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. 3. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source. 4. With these settings, a waveform is output without further software intervention, with a period determined by TCORA and a pulse width determined by TCORB.
TCNTV value H'FF Counter cleared TCORA TCORB H'00 TMOV Time
Figure 12.9 Pulse Output Example
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Section 12 Timer V
12.5.2
Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input
The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 12.10. To set up this output: 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORB. 2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. 3. Set bits TVEG1 and TVEG0 in TCRV1 and set TRGE to select the falling edge of the TRGV input. 4. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source. 5. With these settings, a pulse waveform will be output without further software intervention, with a delay determined by TCORA from the TRGV input, and a pulse width determined by (TCORB - TCORA).
TCNTV value H'FF Counter cleared TCORB TCORA H'00 TRGV Time
TMOV
Compare match A Compare match A
Compare match B clears TCNTV and halts count-up
Compare match B clears TCNTV and halts count-up
Figure 12.10 Example of Pulse Output Synchronized to TRGV Input
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Section 12 Timer V
12.6
Usage Notes
The following types of contention or operation can occur in timer V operation. 1. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 12.11, clearing takes precedence and the write to the counter is not carried out. If counting-up is generated in the T3 state of a TCNTV write cycle, writing takes precedence. If a compare match is generated in the T3 state of a TCORA or TCORB write cycle, the write to TCORA or TCORB takes precedence and the compare match signal is inhibited. Figure 12.12 shows the timing. If compare matches A and B occur simultaneously, any conflict between the output selections for compare match A and compare match B is resolved by the following priority: toggle output > output 1 > output 0. Depending on the timing, TCNTV may be incremented by a switch between different internal clock sources. When TCNTV is internally clocked, an increment pulse is generated from the falling edge of an internal clock signal, that is divided system clock (). Therefore, as shown in figure 12.3 the switch is from a high clock signal to a low clock signal, the switchover is seen as a falling edge, causing TCNTV to increment. TCNTV can also be incremented by a switch between internal and external clocks.
TCNTV write cycle by CPU T1 T2 T3 Address TCNTV address
2.
3.
4.
Internal write signal
Counter clear signal
TCNTV
N
H'00
Figure 12.11 Contention between TCNTV Write and Clear
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Section 12 Timer V
TCORA write cycle by CPU T2 T3 T1 TCORA address
Address
Internal write signal
TCNTV
N
N+1
TCORA
N
M TCORA write data
Compare match signal Inhibited
Figure 12.12 Contention between TCORA Write and Compare Match
Clock before switching
Clock after switching
Count clock
TCNTV
N
N+1
N+2
Write to CKS1 and CKS0
Figure 12.13 Internal Clock Switching and TCNTV Operation
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Section 12 Timer V
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Section 13 Timer W
Section 13 Timer W
The timer W is a 16-bit timer having output compare and input capture functions. Timer W can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. Thus, it can be applied to various systems.
13.1
Features
* Selection of five counter clock sources: four internal clocks (, /2, /4, /8) and an external clock (external events can be counted) * Capability to process up to four pulse outputs or four pulse inputs * Four general registers: Independently assignable output compare or input capture functions Usable as two pairs of registers; one register of each pair operates as a buffer for the output compare or input capture register * Timer input/output functions Waveform output by compare match: Selection of 0 output, 1 output, or toggle output Input capture function: Rising edge, falling edge, or both edges Counter clearing function: Counters can be cleared by compare match PWM mode: Up to three-phase PWM output can be provided with desired duty ratio. * Any initial timer output value can be set * Five interrupt sources Four compare match/input capture interrupts and an overflow interrupt.
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Section 13 Timer W
Table 13.1 summarizes the timer W functions, and figure 13.1 shows a block diagram of timer W. Table 13.1 Timer W Functions
Input/Output Pins Item Count clock General registers (output compare/input capture registers) Counter clearing function Counter FTIOA FTIOB FTIOC FTIOD Internal clocks: , /2, /4, /8 External clock: FTCI Period GRA specified in GRA GRA compare match -- -- 0 1 Toggle Input capture function PWM mode Interrupt sources -- -- -- -- -- Overflow GRA compare match Yes Yes Yes Yes Yes Yes -- Compare match/input capture GRB GRC (buffer register for GRA in buffer mode) -- GRD (buffer register for GRB in buffer mode) --
--
Initial output value setting function Buffer function Compare match output
Yes Yes Yes Yes Yes Yes Yes Compare match/input capture
Yes -- Yes Yes Yes Yes Yes Compare match/input capture
Yes -- Yes Yes Yes Yes Yes Compare match/input capture
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Section 13 Timer W
Internal clock: /2 /4 /8 External clock: FTCI
FTIOA Clock selector Control logic Comparator FTIOB FTIOC FTIOD IRRTW
TIERW
TMRW
TCRW
TSRW
TCNT
TIOR
GRC
GRD
GRA
GRB
[Legend] TMRW: Timer mode register W (8 bits) TCRW: Timer control register W (8 bits) TIERW: Timer interrupt enable register W (8 bits) TSRW: Timer status register W (8 bits) TIOR: Timer I/O control register (8 bits) TCNT: Timer counter (16 bits) GRA: General register A (input capture/output compare register: 16 bits) GRB: General register B (input capture/output compare register: 16 bits) GRC: General register C (input capture/output compare register: 16 bits) GRD: General register D (input capture/output compare register: 16 bits)
Figure 13.1 Block Diagram of Timer W
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Bus interface
Internal data bus
Section 13 Timer W
13.2
Input/Output Pins
Table 13.2 summarizes the timer W pins. Table 13.2 Pin Configuration
Name External clock input Input capture/output compare A Input capture/output compare B Input capture/output compare C Input capture/output compare D Abbreviation FTCI FTIOA FTIOB Input/Output Function Input Input/output Input/output External clock input pin Output pin for GRA output compare or input pin for GRA input capture Output pin for GRB output compare, input pin for GRB input capture, or PWM output pin in PWM mode Output pin for GRC output compare, input pin for GRC input capture, or PWM output pin in PWM mode Output pin for GRD output compare, input pin for GRD input capture, or PWM output pin in PWM mode
FTIOC
Input/output
FTIOD
Input/output
13.3
Register Descriptions
The timer W has the following registers. * * * * * * * * * * * Timer mode register W (TMRW) Timer control register W (TCRW) Timer interrupt enable register W (TIERW) Timer status register W (TSRW) Timer I/O control register 0 (TIOR0) Timer I/O control register 1 (TIOR1) Timer counter (TCNT) General register A (GRA) General register B (GRB) General register C (GRC) General register D (GRD)
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Section 13 Timer W
13.3.1
Timer Mode Register W (TMRW)
TMRW selects the general register functions and the timer output mode.
Bit 7 Bit Name CTS Initial Value 0 R/W R/W Description Counter Start The counter operation is halted when this bit is 0; while it can be performed when this bit is 1. 6 5 BUFEB 1 0 R/W Reserved This bit is always read as 1. Buffer Operation B Selects the GRD function. 0: GRD operates as an input capture/output compare register 1: GRD operates as the buffer register for GRB 4 BUFEA 0 R/W Buffer Operation A Selects the GRC function. 0: GRC operates as an input capture/output compare register 1: GRC operates as the buffer register for GRA 3 2 PWMD 1 0 R/W Reserved This bit is always read as 1. PWM Mode D Selects the output mode of the FTIOD pin. 0: FTIOD operates normally (output compare output) 1: PWM output 1 PWMC 0 R/W PWM Mode C Selects the output mode of the FTIOC pin. 0: FTIOC operates normally (output compare output) 1: PWM output 0 PWMB 0 R/W PWM Mode B Selects the output mode of the FTIOB pin. 0: FTIOB operates normally (output compare output) 1: PWM output
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Section 13 Timer W
13.3.2
Timer Control Register W (TCRW)
TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer initial output levels.
Bit 7 Bit Name CCLR Initial Value 0 R/W R/W Description Counter Clear The TCNT value is cleared by compare match A when this bit is 1. When it is 0, TCNT operates as a freerunning counter. 6 5 4 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0 Select the TCNT clock source. 000: Internal clock: counts on 001: Internal clock: counts on /2 010: Internal clock: counts on /4 011: Internal clock: counts on /8 1xx: Counts on rising edges of the external event (FTCI) When the internal clock source () is selected, subclock sources are counted in subactive and subsleep modes. 3 TOD 0 R/W Timer Output Level Setting D Sets the output value of the FTIOD pin until the first compare match D is generated. 0: Initial output value is 0* 1: Initial output value is 1* 2 TOC 0 R/W Timer Output Level Setting C Sets the output value of the FTIOC pin until the first compare match C is generated. 0: Initial output value is 0* 1: Initial output value is 1* 1 TOB 0 R/W Timer Output Level Setting B Sets the output value of the FTIOB pin until the first compare match B is generated. 0: Initial output value is 0* 1: Initial output value is 1*
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Section 13 Timer W
Bit 0
Bit Name TOA
Initial Value 0
R/W R/W
Description Timer Output Level Setting A Sets the output value of the FTIOA pin until the first compare match A is generated. 0: Initial output value is 0* 1: Initial output value is 1*
[Legend] x: Don't care. Note: * The change of the setting is immediately reflected in the output value.
13.3.3
Timer Interrupt Enable Register W (TIERW)
TIERW controls the timer W interrupt request.
Bit 7 Bit Name OVIE Initial Value 0 R/W R/W Description Timer Overflow Interrupt Enable When this bit is set to 1, FOVI interrupt requested by OVF flag in TSRW is enabled. 6 to 4 3 IMIED All 1 0 R/W Reserved These bits are always read as 1. Input Capture/Compare Match Interrupt Enable D When this bit is set to 1, IMID interrupt requested by IMFD flag in TSRW is enabled. 2 IMIEC 0 R/W Input Capture/Compare Match Interrupt Enable C When this bit is set to 1, IMIC interrupt requested by IMFC flag in TSRW is enabled. 1 IMIEB 0 R/W Input Capture/Compare Match Interrupt Enable B When this bit is set to 1, IMIB interrupt requested by IMFB flag in TSRW is enabled. 0 IMIEA 0 R/W Input Capture/Compare Match Interrupt Enable A When this bit is set to 1, IMIA interrupt requested by IMFA flag in TSRW is enabled.
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Section 13 Timer W
13.3.4
Timer Status Register W (TSRW)
TSRW shows the status of interrupt requests.
Bit 7 Bit Name OVF Initial Value 0 R/W R/W Description Timer Overflow Flag [Setting condition] * * 6 to 4 3 IMFD All 1 0 R/W When TCNT overflows from H'FFFF to H'0000 Read OVF when OVF=1, then write 0 in OVF [Clearing condition] Reserved These bits are always read as 1. Input Capture/Compare Match Flag D [Setting conditions] * * TCNT=GRD when GRD functions as an output compare register The TCNT value is transferred to GRD by an input capture signal when GRD functions as an input capture register Read IMFD when IMFD=1, then write 0 in IMFD
[Clearing condition] * 2 IMFC 0 R/W Input Capture/Compare Match Flag C [Setting conditions] * * TCNT=GRC when GRC functions as an output compare register The TCNT value is transferred to GRC by an input capture signal when GRC functions as an input capture register Read IMFC when IMFC=1, then write 0 in IMFC
[Clearing condition] *
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Section 13 Timer W
Bit 1
Bit Name IMFB
Initial Value 0
R/W R/W
Description Input Capture/Compare Match Flag B [Setting conditions] * * TCNT=GRB when GRB functions as an output compare register The TCNT value is transferred to GRB by an input capture signal when GRB functions as an input capture register Read IMFB when IMFB=1, then write 0 in IMFB
[Clearing condition] * 0 IMFA 0 R/W Input Capture/Compare Match Flag A [Setting conditions] * * TCNT=GRA when GRA functions as an output compare register The TCNT value is transferred to GRA by an input capture signal when GRA functions as an input capture register Read IMFA when IMFA=1, then write 0 in IMFA
[Clearing condition] *
13.3.5
Timer I/O Control Register 0 (TIOR0)
TIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and FTIOB pins.
Bit 7 6 Bit Name IOB2 Initial Value 1 0 R/W R/W Description Reserved This bit is always read as 1. I/O Control B2 Selects the GRB function. 0: GRB functions as an output compare register 1: GRB functions as an input capture register
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Section 13 Timer W
Bit 5 4
Bit Name IOB1 IOB0
Initial Value 0 0
R/W R/W R/W
Description I/O Control B1 and B0 When IOB2 = 0, 00: No output at compare match 01: 0 output to the FTIOB pin at GRB compare match 10: 1 output to the FTIOB pin at GRB compare match 11: Output toggles to the FTIOB pin at GRB compare match When IOB2 = 1, 00: Input capture at rising edge at the FTIOB pin 01: Input capture at falling edge at the FTIOB pin 1x: Input capture at rising edge and falling edge at the FTIOB pin
3 2
IOA2
1 0
R/W
Reserved This bit is always read as 1. I/O Control A2 Selects the GRA function. 0: GRA functions as an output compare register 1: GRA functions as an input capture register
1 0
IOA1 IOA0
0 0
R/W R/W
I/O Control A1 and A0 When IOA2 = 0, 00: No output at compare match 01: 0 output to the FTIOA pin at GRA compare match 10: 1 output to the FTIOA pin at GRA compare match 11: Output toggles to the FTIOA pin at GRA compare match When IOA2 = 1, 00: Input capture at rising edge of the FTIOA pin 01: Input capture at falling edge of the FTIOA pin 1x: Input capture at rising edge and falling edge of the FTIOA pin
[Legend]
X: Don't care.
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Section 13 Timer W
13.3.6
Timer I/O Control Register 1 (TIOR1)
TIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and FTIOD pins.
Bit 7 6 Bit Name IOD2 Initial Value 1 0 R/W R/W Description Reserved This bit is always read as 1. I/O Control D2 Selects the GRD function. 0: GRD functions as an output compare register 1: GRD functions as an input capture register I/O Control D1 and D0 When IOD2 = 0,
00: No output at compare match 01: 0 output to the FTIOD pin at GRD compare match 10: 1 output to the FTIOD pin at GRD compare match 11: Output toggles to the FTIOD pin at GRD compare match When IOD2 = 1, 00: Input capture at rising edge at the FTIOD pin 01: Input capture at falling edge at the FTIOD pin 1x: Input capture at rising edge and falling edge at the FTIOD pin
5 4
IOD1 IOD0
0 0
R/W R/W
3 2
IOC2
1 0
R/W
Reserved This bit is always read as 1. I/O Control C2 Selects the GRC function. 0: GRC functions as an output compare register 1: GRC functions as an input capture register
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Section 13 Timer W
Bit 1 0
Bit Name IOC1 IOC0
Initial Value 0 0
R/W R/W R/W
Description I/O Control C1 and C0 When IOC2 = 0,
00: No output at compare match 01: 0 output to the FTIOC pin at GRC compare match 10: 1 output to the FTIOC pin at GRC compare match 11: Output toggles to the FTIOC pin at GRC compare match
When IOC2 = 1,
00: Input capture to GRC at rising edge of the FTIOC pin 01: Input capture to GRC at falling edge of the FTIOC pin 1x: Input capture to GRC at rising edge and falling edge of the FTIOC pin
[Legend]
X: Don't care.
13.3.7
Timer Counter (TCNT)
TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA by setting the CCLR bit in TCRW to 1. When TCNT overflows (changes from H'FFFF to H'0000), the OVF flag in TSRW is set to 1. If the OVIE bit in TIERW is set to 1 at this time, an interrupt request is generated. TCNT must always be read or written in 16-bit units; 8-bit access is not allowed. TCNT is initialized to H'0000.
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Section 13 Timer W
13.3.8
General Registers A to D (GRA to GRD)
Each general register is a 16-bit readable/writable register that can function as either an outputcompare register or an input-capture register. The function is selected by settings in TIOR0 and TIOR1. When a general register is used as an output-compare register, its value is constantly compared with the TCNT value. When the two values match (a compare match), the corresponding flag (IMFA, IMFB, IMFC, or IMFD) in TSRW is set to 1. An interrupt request is generated at this time, when IMIEA, IMIEB, IMIEC, or IMIED is set to 1. Compare match output can be selected in TIOR. When a general register is used as an input-capture register, an external input-capture signal is detected and the current TCNT value is stored in the general register. The corresponding flag (IMFA, IMFB, IMFC, or IMFD) in TSRW is set to 1. If the corresponding interrupt-enable bit (IMIEA, IMIEB, IMIEC, or IMIED) in TSRW is set to 1 at this time, an interrupt request is generated. The edge of the input-capture signal is selected in TIOR. GRC and GRD can be used as buffer registers of GRA and GRB, respectively, by setting BUFEA and BUFEB in TMRW. For example, when GRA is set as an output-compare register and GRC is set as the buffer register for GRA, the value in the buffer register GRC is sent to GRA whenever compare match A is generated. When GRA is set as an input-capture register and GRC is set as the buffer register for GRA, the value in TCNT is transferred to GRA and the value in GRA is transferred to the buffer register GRC whenever an input capture is generated. GRA to GRD must be written or read in 16-bit units; 8-bit access is not allowed. GRA to GRD are initialized to H'FFFF.
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Section 13 Timer W
13.4
Operation
The timer W has the following operation modes: * Normal Operation * PWM Operation 13.4.1 Normal Operation
TCNT performs free-running or periodic counting operations. After a reset, TCNT is set as a freerunning counter. When the CST bit in TMRW is set to 1, TCNT starts incrementing the count. When the count overflows from H'FFFF to H'0000, the OVF flag in TSRW is set to 1. If the OVIE in TIERW is set to 1, an interrupt request is generated. Figure 13.2 shows free-running counting.
TCNT value H'FFFF
H'0000 CST bit Flag cleared by software OVF
Time
Figure 13.2 Free-Running Counter Operation
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Section 13 Timer W
Periodic counting operation can be performed when GRA is set as an output compare register and bit CCLR in TCRW is set to 1. When the count matches GRA, TCNT is cleared to H'0000, the IMFA flag in TSRW is set to 1. If the corresponding IMIEA bit in TIERW is set to 1, an interrupt request is generated. TCNT continues counting from H'0000. Figure 13.3 shows periodic counting.
TCNT value GRA
H'0000
Time
CST bit Flag cleared by software IMFA
Figure 13.3 Periodic Counter Operation By setting a general register as an output compare register, compare match A, B, C, or D can cause the output at the FTIOA, FTIOB, FTIOC, or FTIOD pin to output 0, output 1, or toggle. Figure 13.4 shows an example of 0 and 1 output when TCNT operates as a free-running counter, 1 output is selected for compare match A, and 0 output is selected for compare match B. When signal is already at the selected output level, the signal level does not change at compare match.
TCNT value H'FFFF GRA GRB H'0000 FTIOA FTIOB No change No change Time No change No change
Figure 13.4 0 and 1 Output Example (TOA = 0, TOB = 1)
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Section 13 Timer W
Figure 13.5 shows an example of toggle output when TCNT operates as a free-running counter, and toggle output is selected for both compare match A and B.
TCNT value H'FFFF GRA GRB H'0000 FTIOA FTIOB Time Toggle output Toggle output
Figure 13.5 Toggle Output Example (TOA = 0, TOB = 1) Figure 13.6 shows another example of toggle output when TCNT operates as a periodic counter, cleared by compare match A. Toggle output is selected for both compare match A and B.
TCNT value Counter cleared by compare match with GRA H'FFFF GRB GRA H'0000 FTIOA FTIOB Time Toggle output Toggle output
Figure 13.6 Toggle Output Example (TOA = 0, TOB = 1)
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Section 13 Timer W
By setting a general register as an input-capture register, the TCNT value can be captured into a general register (GRA, GRB, GRC, or GRD) when a signal level changes at an input-capture pin (FTIOA, FTIOB, FTIOC, or FTIOD). Capture can take place on the rising edge, falling edge, or both edges. By using the input-capture function, the pulse width and periods can be measured. Figure 13.7 shows an example of input capture when both edges of FTIOA and the falling edge of FTIOB are selected as capture edges. TCNT operates as a free-running counter.
TCNT value H'FFFF H'F000 H'AA55 H'55AA H'1000 H'0000 Time
FTIOA
GRA
H'1000
H'F000
H'55AA
FTIOB GRB H'AA55
Figure 13.7 Input Capture Operating Example
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Section 13 Timer W
Figure 13.8 shows an example of buffer operation when the GRA is set as an input-capture register and GRC is set as the buffer register for GRA. TCNT operates as a free-running counter, and FTIOA captures both rising and falling edge of the input signal. Due to the buffer operation, the GRA value is transferred to GRC by input-capture A and the TCNT value is stored in GRA.
TCNT value H'FFFF H'DA91 H'5480 H'0245 H'0000 FTIOA
Time
GRA GRC
H'0245
H'5480 H'0245
H'DA91 H'5480
Figure 13.8 Buffer Operation Example (Input Capture)
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Section 13 Timer W
13.4.2
PWM Operation
In PWM mode, PWM waveforms are generated by using GRA as the cycle register and GRB, GRC, and GRD as duty registers. PWM waveforms are output from the FTIOB, FTIOC, and FTIOD pins. Up to three-phase PWM waveforms can be output. In PWM mode, a general register functions as an output compare register automatically. The output level of each pin depends on the corresponding timer output level set bit (TOB, TOC, TOD) in TCRW. When TOB is 1, the FTIOB output goes to 1 at compare match A and to 0 at compare match B. When TOB is 0, the FTIOB output goes to 0 at compare match A and to 1 at compare match B. Thus the compare match output level settings in TIOR0 and TIOR1 are ignored for the output pin set to PWM mode. If the same value is set in the cycle register and the duty register, the output does not change when a compare match occurs. Figure 13.9 shows an example of operation in PWM mode. The output signals go to 1 and TCNT is cleared at compare match A, and the output signals go to 0 at compare match B, C, and D (TOB, TOC, and TOD = 1).
TCNT value GRA GRB GRC GRD H'0000 FTIOB FTIOC Time
Counter cleared by compare match A
FTIOD
Figure 13.9 PWM Mode Example (1)
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Section 13 Timer W
Figure 13.10 shows another example of operation in PWM mode. The output signals go to 0 and TCNT is cleared at compare match A, and the output signals go to 1 at compare match B, C, and D (TOB, TOC, and TOD = 0).
TCNT value Counter cleared by compare match A GRA GRB GRC GRD H'0000 FTIOB FTIOC Time
FTIOD
Figure 13.10 PWM Mode Example (2)
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Section 13 Timer W
Figure 13.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB outputs 1 at compare match B and 0 at compare match A. Due to the buffer operation, the FTIOB output level changes and the value of buffer register GRD is transferred to GRB whenever compare match B occurs. This procedure is repeated every time compare match B occurs.
TCNT value GRA H'0200
H'0450
H'0520
GRB H'0000 GRD
Time H'0200 H'0450 H'0520
GRB
H'0200
H'0450
H'0520
FTIOB
Figure 13.11 Buffer Operation Example (Output Compare)
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Section 13 Timer W
Figures 13.12 and 13.13 show examples of the output of PWM waveforms with duty cycles of 0% and 100%.
TCNT value Write to GRB GRA
GRB H'0000 Duty 0%
Write to GRB Time
FTIOB
TCNT value Write to GRB GRA
Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB Write to GRB
GRB H'0000 Duty 100% Time
FTIOB
TCNT value Write to GRB GRA
Output does not change when cycle register and duty register compare matches occur simultaneously.
Write to GRB Write to GRB Time Duty 100% Duty 0%
GRB H'0000
FTIOB
Figure 13.12 PWM Mode Example (TOB = 0, TOC = 0, TOD = 0: Initial Output Values are Set to 0)
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Section 13 Timer W
TCNT value Write to GRB GRA
GRB H'0000 Duty 100%
Write to GRB Time
FTIOB
TCNT value Write to GRB GRA
Output does not change when cycle register and duty register compare matches occur simultaneously.
Write to GRB Write to GRB
GRB H'0000 Duty 0% Time
FTIOB
TCNT value Write to GRB GRA
Output does not change when cycle register and duty register compare matches occur simultaneously.
Write to GRB Write to GRB Time Duty 0% Duty 100%
GRB H'0000
FTIOB
Figure 13.13 PWM Mode Example (TOB = 1, TOC = 1,and TOD = 1: Initial Output Values are Set to 1)
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Section 13 Timer W
13.5
13.5.1
Operation Timing
TCNT Count Timing
Figure 13.14 shows the TCNT count timing when the internal clock source is selected. Figure 13.15 shows the timing when the external clock source is selected. The pulse width of the external clock signal must be at least two system clock () cycles; shorter pulses will not be counted correctly.
Internal clock TCNT input clock TCNT N N+1 N+2 Rising edge
Figure 13.14 Count Timing for Internal Clock Source
External clock TCNT input clock TCNT N N+1 N+2 Rising edge Rising edge
Figure 13.15 Count Timing for External Clock Source
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Section 13 Timer W
13.5.2
Output Compare Timing
The compare match signal is generated in the last state in which TCNT and the general register match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD). When TCNT matches a general register, the compare match signal is generated only after the next counter clock pulse is input. Figure 13.16 shows the output compare timing.
TCNT input clock TCNT N N+1
GRA to GRD Compare match signal FTIOA to FTIOD
N
Figure 13.16 Output Compare Output Timing
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Section 13 Timer W
13.5.3
Input Capture Timing
Input capture on the rising edge, falling edge, or both edges can be selected through settings in TIOR0 and TIOR1. Figure 13.17 shows the timing when the falling edge is selected. The pulse width of the input capture signal must be at least two system clock () cycles; shorter pulses will not be detected correctly.
Input capture input Input capture signal TCNT GRA to GRD N-1 N N+1 N+2
N
Figure 13.17 Input Capture Input Signal Timing 13.5.4 Timing of Counter Clearing by Compare Match
Figure 13.18 shows the timing when the counter is cleared by compare match A. When the GRA value is N, the counter counts from 0 to N, and its cycle is N + 1.
Compare match signal
TCNT
N
H'0000
GRA
N
Figure 13.18 Timing of Counter Clearing by Compare Match
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Section 13 Timer W
13.5.5
Buffer Operation Timing
Figures 13.19 and 13.20 show the buffer operation timing.
Compare match signal TCNT N N+1
GRC, GRD
M
GRA, GRB
M
Figure 13.19 Buffer Operation Timing (Compare Match)
Input capture signal TCNT N N+1
GRA, GRB
M
N
N+1
GRC, GRD
M
N
Figure 13.20 Buffer Operation Timing (Input Capture)
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Section 13 Timer W
13.5.6
Timing of IMFA to IMFD Flag Setting at Compare Match
If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general register. The compare match signal is generated in the last state in which the values match (when TCNT changes from the matching value to the next value). Therefore, when TCNT matches a general register, the compare match signal is generated only after the next TCNT clock pulse is input. Figure 13.21 shows the timing of the IMFA to IMFD flag setting at compare match.
TCNT input clock TCNT N N+1
GRA to GRD Compare match signal IMFA to IMFD IRRTW
N
Figure 13.21 Timing of IMFA to IMFD Flag Setting at Compare Match
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Section 13 Timer W
13.5.7
Timing of IMFA to IMFD Setting at Input Capture
If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure 13.22 shows the timing of the IMFA to IMFD flag setting at input capture.
Input capture signal TCNT N
GRA to GRD
N
IMFA to IMFD
IRRTW
Figure 13.22 Timing of IMFA to IMFD Flag Setting at Input Capture 13.5.8 Timing of Status Flag Clearing
When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. Figure 13.23 shows the status flag clearing timing.
TSRW write cycle T1 T2 Address TSRW address
Write signal IMFA to IMFD
IRRTW
Figure 13.23 Timing of Status Flag Clearing by CPU
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Section 13 Timer W
13.6
Usage Notes
The following types of contention or operation can occur in timer W operation. 1. The pulse width of the input clock signal and the input capture signal must be at least two system clock () cycles; shorter pulses will not be detected correctly. 2. Writing to registers is performed in the T2 state of a TCNT write cycle. If counter clear signal occurs in the T2 state of a TCNT write cycle, clearing of the counter takes priority and the write is not performed, as shown in figure 13.24. If counting-up is generated in the TCNT write cycle to contend with the TCNT counting-up, writing takes precedence. 3. Depending on the timing, TCNT may be incremented by a switch between different internal clock sources. When TCNT is internally clocked, an increment pulse is generated from the rising edge of an internal clock signal, that is divided system clock (). Therefore, as shown in figure 13.25 the switch is from a low clock signal to a high clock signal, the switchover is seen as a rising edge, causing TCNT to increment. 4. If timer W enters module standby mode while an interrupt request is generated, the interrupt request cannot be cleared. Before entering module standby mode, disable interrupt requests.
TCNT write cycle T2 T1 TCNT address
Address
Write signal Counter clear signal N H'0000
TCNT
Figure 13.24 Contention between TCNT Write and Clear
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Section 13 Timer W
Previous clock New clock
Count clock
TCNT
N
N+1
N+2
N+3
The change in signal level at clock switching is assumed to be a rising edge, and TCNT increments the count.
Figure 13.25 Internal Clock Switching and TCNT Operation
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Section 13 Timer W
5. The TOA to TOD bits in TCRW decide the value of the FTIO pin, which is output until the first compare match occurs. Once a compare match occurs and this compare match changes the values of FTIOA to FTIOD output, the values of the FTIOA to FTIOD pin output and the values read from the TOA to TOD bits may differ. Moreover, when the writing to TCRW and the generation of the compare match A to D occur at the same timing, the writing to TCRW has the priority. Thus, output change due to the compare match is not reflected to the FTIOA to FTIOD pins. Therefore, when bit manipulation instruction is used to write to TCRW, the values of the FTIOA to FTIOD pin output may result in an unexpected result. When TCRW is to be written to while compare match is operating, stop the counter once before accessing to TCRW, read the port 8 state to reflect the values of FTIOA to FTIOD output, to TOA to TOD, and then restart the counter. Figure 13.26 shows an example when the compare match and the bit manipulation instruction to TCRW occur at the same timing.
TOCR has been set to H'06. Compare match B and compare match C are used. The FTIOB pin is in the 1 output state, and is set to the toggle output or the 0 output by compare match B. When BCLR#2, @TOCR is executed to clear the TOC bit (the FTIOC0 signal is low) and compare match B occurs at the same timing as shown below, the H'02 writing to TOCR has priority and compare match B does not drive the FTIOB signal low; the FTIOB signal remains high. Bit TCRW Set value 7 CCLR 0 6 CKS2 0 5 CKS1 0 4 CKS0 0 3 TOD 0 2 TOC 1 1 TOB 1 0 TOA 0
BCLR#2, @TCRW (1) TCRW read operation: Read H'06 (2) Modify operation: Modify H'06 to H'02 (3) Write operation to TOCR: Write H'02
TCRW write signal Compare match signal B
FTIOB pin
Expected output Remains high because the 1 writing to TOB has priority
Figure 13.26 When Compare Match and Bit Manipulation Instruction to TCRW Occur at the Same Timing
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Section 14 Timer Z
Section 14 Timer Z
The timer Z has a 16-bit timer with two channels. Figures 14.1, 14.2, and 14.3 show the block diagrams of entire timer Z, its channel 0, and its channel 1, respectively. For details on the timer Z functions, see table 14.1.
14.1
Features
* Capability to process up to eight inputs/outputs * Eight general registers (GR): four registers for each channel Independently assignable output compare or input capture functions * Selection of five counter clock sources: four internal clocks (, /2, /4, and /8) and an external clock * Seven selectable operating modes Output compare function Selection of 0 output, 1 output, or toggle output Input capture function Rising edge, falling edge, or both edges Synchronous operation Timer counters_0 and _1 (TCNT_0 and TCNT_1) can be written simultaneously. Simultaneous clearing by compare match or input capture is possible. PWM mode Up to six-phase PWM output can be provided with desired duty ratio. Reset synchronous PWM mode Three-phase PWM output for normal and counter phases Complementary PWM mode Three-phase PWM output for non-overlapped normal and counter phases The A/D conversion start trigger can be set for PWM cycles. Buffer operation The input capture register can be consisted of double buffers. The output compare register can automatically be modified. * High-speed access by the internal 16-bit bus 16-bit TCNT and GR registers can be accessed in high speed by a 16-bit bus interface * Any initial timer output value can be set * Output of the timer is disabled by external trigger
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Section 14 Timer Z
* Eleven interrupt sources Four compare match/input capture interrupts and an overflow interrupt are available for each channel. An underflow interrupt can be set for channel 1. Table 14.1 Timer Z Functions
Item Count clock General registers (output compare/input capture registers) Buffer register I/O pins Counter clearing function Channel 0 Internal clocks: , /2, /4, /8 External clock: FTIOA0 (TCLK) GRA_0, GRB_0, GRC_0, GRD_0 GRA_1, GRB_1, GRC_1, GRD_1 Channel 1
GRC_0, GRD_0 FTIOA0, FTIOB0, FTIOC0, FTIOD0 Compare match/input capture of GRA_0, GRB_0, GRC_0, or GRD_0 Yes Yes Yes Yes Yes Yes Yes Yes Yes Compare match/input capture A0 to D0 Overflow
GRC_1, GRD_1 FTIOA1, FTIOB1, FTIOC1, FTIOD1 Compare match/input capture of GRA_1, GRB_1, GRC_1, or GRD_1 Yes Yes Yes Yes Yes Yes Yes Yes Yes Compare match/input capture A1 to D1 Overflow Underflow
Compare match output
0 output 1 output output
Input capture function Synchronous operation PWM mode Reset synchronous PWM mode Complementary PWM mode Buffer function Interrupt sources
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Section 14 Timer Z
ITMZ0 FTIOA0 FTIOB0 FTIOC0 FTIOD0 FTIOA1 FTIOB1 FTIOC1 FTIOD1 , /2, /4, /8 Control logic ITMZ1
ADTRG
TSTR TMDR Channel 0 timer Channel 1 timer TPMR TFCR TOER TOCR
Module data bus
[Legend] TSTR: TMDR: TPMR: TFCR: TOER: TOCR: ADTRG: ITMZ0: ITMZ1:
Timer start register (8 bits) Timer mode register (8 bits) Timer PWM mode register (8 bits) Timer function control register (8 bits) Timer output master enable register (8 bits) Timer output control register (8 bits) A/D conversion start trigger output signal Channel 0 interrupt Channel 1 interrupt
Figure 14.1 Timer Z Block Diagram
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Section 14 Timer Z
FTIOA0 , /2, /4, /8 FTIOB0 FTIOC0 FTIOD0 ITMZ0 Comparator
Clock select Control logic
TIORC_0
TIORA_0
Module data bus [Legend] TCNT_0 GRA_0, GRB_0: : GRC_0, GRD_0 TCR_0: : TIORA_0: TIORC_0: TSR_0: TIER_0: POCR_0: ITMZ0:
Timer counter_0 (16 bits) General registers A_0, B_0, C_0, and D_0 (input capture/output compare registers: 16 bits x 4) Timer control register_0 (8 bits) Timer I/O control register A_0 (8 bits) Timer I/O control register C_0 (8 bits) Timer status register_0 (8 bits) Timer interrupt enable register_0 (8 bits) PWM mode output level control register_0 (8 bits) Channel 0 interrupt
Figure 14.2 Timer Z (Channel 0) Block Diagram
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POCR_0
TCNT_0
TIER_0
GRC_0
GRD_0
GRA_0
GRB_0
TCR_0
TSR_0
Section 14 Timer Z
FTIOA1 , /2, /4, /8 FTIOB1 FTIOC1 FTIOD1 ITMZ1 Comparator
Clock select Control logic
TIORC_1
TIORA_1
Module data bus [Legend] TCNT_1: GRA_1, GRB_1: GRC_1, GRD_1: TCR_1: TIORA_1: TIORC_1: TSR_1: TIER_1: POCR_1: ITMZ1:
Timer counter_1 (16 bits) General registers A_1, B_1, C_1, and D_1 (input capture/output compare registers: 16 bits x 4) Timer control register_1 (8 bits) Timer I/O control register A_1 (8 bits) Timer I/O control register C_1 (8 bits) Timer status register_1 (8 bits) Timer interrupt enable register_1 (8 bits) PWM mode output level control register_1 (8 bits) Channel 1 interrupt
Figure 14.3 Timer Z (Channel 1) Block Diagram
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POCR_1
TCNT_1
TIER_1
GRC_1
GRD_1
GRA_1
GRB_1
TCR_1
TSR_1
Section 14 Timer Z
14.2
Input/Output Pins
Table 14.2 summarizes the timer Z pins. Table 14.2 Pin Configuration
Name Input capture/output compare A0 Input capture/output compare B0 Input capture/output compare C0 Abbreviation FTIOA0 Input/Output Function Input/output GRA_0 output compare output, GRA_0 input capture input, or external clock input (TCLK) GRB_0 output compare output, GRB_0 input capture input, or PWM output GRC_0 output compare output, GRC_0 input capture input, or PWM synchronous output (in reset synchronous PWM and complementary PWM modes) GRD_0 output compare output, GRD_0 input capture input, or PWM output GRA_1 output compare output, GRA_1 input capture input, or PWM output (in reset synchronous PWM and complementary PWM modes) GRB_1 output compare output, GRB_1 input capture input, or PWM output GRC_1 output compare output, GRC_1 input capture input, or PWM output GRD_1 output compare output, GRD_1 input capture input, or PWM output
FTIOB0 FTIOC0
Input/output Input/output
Input capture/output compare D0 Input capture/output compare A1
FTIOD0 FTIOA1
Input/output Input/output
Input capture/output compare B1 Input capture/output compare C1 Input capture/output compare D1
FTIOB1 FTIOC1 FTIOD1
Input/output Input/output Input/output
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Section 14 Timer Z
14.3
Register Descriptions
The timer Z has the following registers. Common * * * * * * Timer start register (TSTR) Timer mode register (TMDR) Timer PWM mode register (TPMR) Timer function control register (TFCR) Timer output master enable register (TOER) Timer output control register (TOCR)
Channel 0 * * * * * * * * * * * Timer control register_0 (TCR_0) Timer I/O control register A_0 (TIORA_0) Timer I/O control register C_0 (TIORC_0) Timer status register_0 (TSR_0) Timer interrupt enable register_0 (TIER_0) PWM mode output level control register_0 (POCR_0) Timer counter_0 (TCNT_0) General register A_0 (GRA_0) General register B_0 (GRB_0) General register C_0 (GRC_0) General register D_0 (GRD_0)
Channel 1 * * * * * * * * * Timer control register_1 (TCR_1) Timer I/O control register A_1 (TIORA_1) Timer I/O control register C_1 (TIORC_1) Timer status register_1 (TSR_1) Timer interrupt enable register_1 (TIER_1) PWM mode output level control register_1 (POCR_1) Timer counter_1 (TCNT_1) General register A_1 (GRA_1) General register B_1 (GRB_1)
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Section 14 Timer Z
* General register C_1 (GRC_1) * General register D_1 (GRD_1) 14.3.1 Timer Start Register (TSTR)
TSTR selects the operation/stop for the TCNT counter.
Bit 7 to 2 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1, and cannot be modified. 1 STR1 0 R/W Channel 1 Counter Start 0: TCNT_1 halts counting 1: TCNT_1 starts counting 0 STR0 0 R/W Channel 0 Counter Start 0: TCNT_0 halts counting 1: TCNT_0 starts counting
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Section 14 Timer Z
14.3.2
Timer Mode Register (TMDR)
TMDR selects buffer operation settings and synchronized operation.
Bit 7 Bit Name BFD1 Initial Value 0 R/W R/W Description Buffer Operation D1 0: GRD_1 operates normally 1: GRB_1 and GRD_1 are used together for buffer operation 6 BFC1 0 R/W Buffer Operation C1 0: GRC_1 operates normally 1: GRA_1 and GRD_1 are used together for buffer operation 5 BFD0 0 R/W Buffer Operation D0 0: GRD_0 operates normally 1: GRB_0 and GRD_0 are used together for buffer operation 4 BFC0 0 R/W Buffer Operation C0 0: GRC_0 operates normally 1: GRA_0 and GRC_0 are used together for buffer operation 3 to 1 All 1 Reserved These bits are always read as 1, and cannot be modified. 0 SYNC 0 R/W Timer Synchronization 0: TCNT_1 and TCNT_0 operate as a different timer 1: TCNT_1 and TCNT_0 are synchronized TCNT_1 and TCNT_0 can be pre-set or cleared synchronously
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Section 14 Timer Z
14.3.3
Timer PWM Mode Register (TPMR)
TPMR sets the pin to enter PWM mode.
Bit 7 6 Bit Name PWMD1 Initial Value 1 0 R/W R/W Description Reserved This bit is always read as 1, and cannot be modified. PWM Mode D1 0: FTIOD1 operates normally 1: FTIOD1 operates in PWM mode 5 PWMC1 0 R/W PWM Mode C1 0: FTIOC1 operates normally 1: FTIOC1 operates in PWM mode 4 PWMB1 0 R/W PWM Mode B1 0: FTIOB1 operates normally 1: FTIOB1 operates in PWM mode 3 2 PWMD0 1 0 R/W Reserved This bit is always read as 1, and cannot be modified. PWM Mode D0 0: FTIOD0 operates normally 1: FTIOD0 operates in PWM mode 1 PWMC0 0 R/W PWM Mode C0 0: FTIOC0 operates normally 1: FTIOC0 operates in PWM mode 0 PWMB0 0 R/W PWM Mode B0 0: FTIOB0 operates normally 1: FTIOB0 operates in PWM mode
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Section 14 Timer Z
14.3.4
Timer Function Control Register (TFCR)
TFCR selects the settings and output levels for each operating mode.
Bit 7 6 Bit Name STCLK Initial Value 1 0 R/W R/W Description Reserved This bit is always read as 1. External Clock Input Select 0: External clock input is disabled 1: External clock input is enabled 5 ADEG 0 R/W A/D Trigger Edge Select A/D module should be set to start an A/D conversion by the external trigger 0: A/D trigger at the crest in complementary PWM mode 1: A/D trigger at the trough in complementary PWM mode 4 ADTRG 0 R/W External Trigger Disable 0: A/D trigger for PWM cycles is disabled in complementary PWM mode 1: A/D trigger for PWM cycles is enabled in complementary PWM mode 3 OLS1 0 R/W Output Level Select 1 Selects the counter-phase output levels in reset synchronous PWM mode or complementary PWM mode. 0: Initial output is high and the active level is low. 1: Initial output is low and the active level is high. 2 OLS0 0 R/W Output Level Select 0 Selects the normal-phase output levels in reset synchronous PWM mode or complementary PWM mode. 0: Initial output is high and the active level is low. 1: Initial output is low and the active level is high. Figure 14.4 shows an example of outputs in reset synchronous PWM mode and complementary PWM mode when OLS1 = 0 and OLS0 = 0.
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Section 14 Timer Z
Bit 1 0
Bit Name CMD1 CMD0
Initial Value 0 0
R/W R/W R/W
Description Combination Mode 1 and 0 00: Channel 0 and channel 1 operate normally 01: Channel 0 and channel 1 are used together to operate in reset synchronous PWM mode 10: Channel 0 and channel 1 are used together to operate in complementary PWM mode (transferred at the trough) 11: Channel 0 and channel 1 are used together to operate in complementary PWM mode (transferred at the crest) Note: When reset synchronous PWM mode or complementary PWM mode is selected by these bits, this setting has the priority to the settings for PWM mode by each bit in TPMR. Stop TCNT_0 and TCNT_1 before making settings for reset synchronous PWM mode or complementary PWM mode.
TCNT_0 TCNT_1
Normal phase Active level Counter phase
Normal phase Counter phase Initial output Initial output Active level Complementary PWM mode
Active level
Active level Reset synchronous PWM mode
Note: Write H'00 to TOCR to start initial outputs after stopping the counter.
Figure 14.4 Example of Outputs in Reset Synchronous PWM Mode and Complementary PWM Mode
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Section 14 Timer Z
14.3.5
Timer Output Master Enable Register (TOER)
TOER enables/disables the outputs for channel 0 and channel 1. When WKP4 is selected for inputs, if a low level signal is input to WKP4, the bits in TOER are set to 1 to disable the output for timer Z.
Bit 7 Bit Name ED1 Initial Value 1 R/W R/W Description Master Enable D1 0: FTIOD1 pin output is enabled according to the TPMR, TFCR, and TIORC_1 settings 1: FTIOD1 pin output is disabled regardless of the TPMR, TFCR, and TIORC_1 settings (FTIOD1 pin is operated as an I/O port). 6 EC1 1 R/W Master Enable C1 0: FTIOC1 pin output is enabled according to the TPMR, TFCR, and TIORC_1 settings 1: FTIOC1 pin output is disabled regardless of the TPMR, TFCR, and TIORC_1 settings (FTIOC1 pin is operated as an I/O port). 5 EB1 1 R/W Master Enable B1 0: FTIOB1 pin output is enabled according to the TPMR, TFCR, and TIORA_1 settings 1: FTIOB1 pin output is disabled regardless of the TPMR, TFCR, and TIORA_1 settings (FTIOB1 pin is operated as an I/O port). 4 EA1 1 R/W Master Enable A1 0: FTIOA1 pin output is enabled according to the TPMR, TFCR, and TIORA_1 settings 1: FTIOA1 pin output is disabled regardless of the TPMR, TFCR, and TIORA_1 settings (FTIOA1 pin is operated as an I/O port). 3 ED0 1 R/W Master Enable D0 0: FTIOD0 pin output is enabled according to the TPMR, TFCR, and TIORC_0 settings 1: FTIOD0 pin output is disabled regardless of the TPMR, TFCR, and TIORC_0 settings (FTIOD0 pin is operated as an I/O port).
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Section 14 Timer Z
Bit 2
Bit Name EC0
Initial Value 1
R/W R/W
Description Master Enable C0 0: FTIOC0 pin output is enabled according to the TPMR, TFCR, and TIORC_0 settings 1: FTIOC0 pin output is disabled regardless of the TPMR, TFCR, and TIORC_0 settings (FTIOC0 pin is operated as an I/O port).
1
EB0
1
R/W
Master Enable B0 0: FTIOB0 pin output is enabled according to the TPMR, TFCR, and TIORA_0 settings 1: FTIOB0 pin output is disabled regardless of the TPMR, TFCR, and TIORA_0 settings (FTIOB0 pin is operated as an I/O port).
0
EA0
1
R/W
Master Enable A0 0: FTIOA0 pin output is enabled according to the TPMR, TFCR, and TIORA_0 settings 1: FTIOA0 pin output is disabled regardless of the TPMR, TFCR, and TIORA_0 settings (FTIOA0 pin is operated as an I/O port).
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Section 14 Timer Z
14.3.6
Timer Output Control Register (TOCR)
TOCR selects the initial outputs before the first occurrence of a compare match. Note that bits OLS1 and OLS0 in TFCR set these initial outputs in reset synchronous PWM mode and complementary PWM mode.
Bit 7 Bit Name TOD1 Initial Value 0 R/W R/W Description Output Level Select D1 0: 0 output at the FTIOD1 pin* 1: 1 output at the FTIOD1 pin* 6 TOC1 0 R/W Output Level Select C1 0: 0 output at the FTIOC1 pin* 1: 1 output at the FTIOC1 pin* 5 TOB1 0 R/W Output Level Select B1 0: 0 output at the FTIOB1 pin* 1: 1 output at the FTIOB1 pin* 4 TOA1 0 R/W Output Level Select A1 0: 0 output at the FTIOA1 pin* 1: 1 output at the FTIOA1 pin* 3 TOD0 0 R/W Output Level Select D0 0: 0 output at the FTIOD0 pin* 1: 1 output at the FTIOD0 pin* 2 TOC0 0 R/W Output Level Select C0 0: 0 output at the FTIOC0 pin* 1: 1 output at the FTIOC0 pin* 1 TOB0 0 R/W Output Level Select B0 0: 0 output at the FTIOB0 pin* 1: 1 output at the FTIOB0 pin* 0 TOA0 0 R/W Output Level Select A0 0: 0 output at the FTIOA0 pin* 1: 1 output at the FTIOA0 pin* Note: * The change of the setting is immediately reflected in the output value.
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Section 14 Timer Z
14.3.7
Timer Counter (TCNT)
The timer Z has two TCNT counters (TCNT_0 and TCNT_1), one for each channel. The TCNT counters are 16-bit readable/writable registers that increment/decrement according to input clocks. Input clocks can be selected by bits TPSC2 to TPSC0 in TCR. TCNT0 and TCNT 1 increment/decrement in complementary PWM mode, while they only increment in other modes. The TCNT counters are initialized to H'0000 by compare matches with corresponding GRA, GRB, GRC, or GRD, or input captures to GRA, GRB, GRC, or GRD (counter clearing function). When the TCNT counters overflow, an OVF flag in TSR for the corresponding channel is set to 1. When TCNT_1 underflows, an UDF flag in TSR is set to 1. The TCNT counters cannot be accessed in 8bit units; they must always be accessed as a 16-bit unit. TCNT is initialized to H'0000. 14.3.8 General Registers A, B, C, and D (GRA, GRB, GRC, and GRD)
GR are 16-bit registers. Timer Z has eight general registers (GR), four for each channel. The GR registers are dual function 16-bit readable/writable registers, functioning as either output compare or input capture registers. Functions can be switched by TIORA and TIORC. The values in GR and TCNT are constantly compared with each other when the GR registers are used as output compare registers. When the both values match, the IMFA to IMFD flags in TSR are set to 1. Compare match outputs can be selected by TIORA and TIORC. When the GR registers are used as input capture registers, the TCNT value is stored after detecting external signals. At this point, IMFA to IMFD flags in the corresponding TSR are set to 1. Detection edges for input capture signals can be selected by TIORA and TIORC. When PWM mode, complementary PWM mode, or reset synchronous PWM mode is selected, the values in TIORA and TIORC are ignored. Upon reset, the GR registers are set as output compare registers (no output) and initialized to H'FFFF. The GR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.
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Section 14 Timer Z
14.3.9
Timer Control Register (TCR)
The TCR registers select a TCNT counter clock, an edge when an external clock is selected, and counter clearing sources. Timer Z has a total of two TCR registers, one for each channel.
Bit 7 6 5 Bit Name CCLR2 CCLR1 CCLR0 Initial Value 0 0 0 R/W R/W R/W R/W Description Counter Clear 2 to 0 000: Disables TCNT clearing 001: Clears TCNT by GRA compare match/input 1 capture* 010: Clears TCNT by GRB compare match/input 1 capture* 011: Synchronization clear; Clears TCNT in synchronous with counter clearing of the other channel's timer*2 100: Disables TCNT clearing 101: Clears TCNT by GRC compare match/input 1 capture* 110: Clears TCNT by GRD compare match/input 1 capture* 111: Synchronization clear; Clears TCNT in synchronous with counter clearing of the other channel's timer*2 4 3 CKEG1 CKEG0 0 0 R/W R/W Clock Edge 1 and 0 00: Count at rising edge 01: Count at falling edge 1X: Count at both edges 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Time Prescaler 2 to 0 000: Internal clock: count by 001: Internal clock: count by /2 010: Internal clock: count by /4 011: Internal clock: count by /8 1XX: External clock: count by FTIOA0 (TCLK) pin input Notes: 1. When GR functions as an output compare register, TCNT is cleared by compare match. When GR functions as input capture, TCNT is cleared by input capture. 2. Synchronous operation is set by TMDR. 3. X: Don't care
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Section 14 Timer Z
14.3.10 Timer I/O Control Register (TIORA and TIORC) The TIOR registers control the general registers (GR). Timer Z has four TIOR registers (TIORA_0, TIORA_1, TIORC_0, and TIORC_1), two for each channel. In PWM mode including complementary PWM mode and reset synchronous PWM mode, the settings of TIOR are invalid. TIORA: TIORA selects whether GRA or GRB is used as an output compare register or an input capture register. When an output compare register is selected, the output setting is selected. When an input capture register is selected, an input edge of an input capture signal is selected. TIORA also selects the function of FTIOA or FTIOB pin.
Bit 7 6 5 4 Bit Name IOB2 IOB1 IOB0 Initial Value 1 0 0 0 R/W R/W R/W R/W Description Reserved This bit is always read as 1. I/O Control B2 to B0 GRB is an output compare register: 000: Disables pin output by compare match 001: 0 output by GRB compare match 010: 1 output by GRB compare match 011: Toggle output by GRB compare match GRB is an input capture register: 100: Input capture to GRB at the rising edge 101: Input capture to GRB at the falling edge 11X: Input capture to GRB at both rising and falling edges Reserved This bit is always read as 1. I/O Control A2 to A0 GRA is an output compare register: 000: Disables pin output by compare match 001: 0 output by GRA compare match 010: 1 output by GRA compare match 011: Toggle output by GRA compare match GRA is an input capture register: 100: Input capture to GRA at the rising edge 101: Input capture to GRA at the falling edge 11X: Input capture to GRA at both rising and falling edges
3 2 1 0
IOA2 IOA1 IOA0
1 0 0 0
R/W R/W R/W
[Legend] X:
Don't care
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Section 14 Timer Z
TIORC: TIORC selects whether GRC or GRD is used as an output compare register or an input capture register. When an output compare register is selected, the output setting is selected. When an input capture register is selected, an input edge of an input capture signal is selected. TIORC also selects the function of FTIOC or FTIOD pin.
Bit 7 6 5 4 Bit Name IOD2 IOD1 IOD0 Initial Value 1 0 0 0 R/W R/W R/W R/W Description Reserved This bit is always read as 1. I/O Control D2 to D0 GRD is an output compare register: 000: Disables pin output by compare match 001: 0 output by GRD compare match 010: 1 output by GRD compare match 011: Toggle output by GRD compare match GRD is an input capture register: 100: Input capture to GRD at the rising edge 101: Input capture to GRD at the falling edge 11X: Input capture to GRD at both rising and falling edges 3 2 1 0 IOC2 IOC1 IOC0 1 0 0 0 R/W R/W R/W Reserved This bit is always read as 1. I/O Control C2 to C0 GRC is an output compare register: 000: Disables pin output by compare match 001: 0 output by GRC compare match 010: 1 output by GRC compare match 011: Toggle Output by GRC compare match GRC is an input capture register: 100: Input capture to GRC at the rising edge 101: Input capture to GRC at the falling edge 11X: Input capture to GRC at both rising and falling edges [Legend] X: Don't care
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Section 14 Timer Z
14.3.11 Timer Status Register (TSR) TSR indicates generation of an overflow/underflow of TCNT and a compare match/input capture of GRA, GRB, GRC, and GRD. These flags are interrupt sources. If an interrupt is enabled by a corresponding bit in TIER, TSR requests an interrupt for the CPU. Timer Z has two TSR registers, one for each channel.
Bit 7, 6 5 Bit Name UDF* Initial Value All 1 0 R/W R/W Description Reserved These bits are always read as 1. Underflow Flag [Setting condition] * * 4 OVF 0 R/W When TCNT_1 underflows When 0 is written to UDF after reading UDF = 1 [Clearing condition] Overflow Flag [Setting condition] * * 3 IMFD 0 R/W When the TCNT value underflows When 0 is written to OVF after reading OVF = 1 [Clearing condition] Input Capture/Compare Match Flag D [Setting conditions] * * When TCNT = GRD and GRD is functioning as output compare register When TCNT value is transferred to GRD by input capture signal and GRD is functioning as input capture register When 0 is written to IMFD after reading IMFD = 1
[Clearing condition] *
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Section 14 Timer Z
Bit 2
Bit Name IMFC
Initial Value 0
R/W R/W
Description Input Capture/Compare Match Flag C [Setting conditions] * * When TCNT = GRC and GRC is functioning as output compare register When TCNT value is transferred to GRC by input capture signal and GRC is functioning as input capture register When 0 is written to IMFC after reading IMFC = 1
[Clearing condition] * 1 IMFB 0 R/W Input Capture/Compare Match Flag B [Setting conditions] * * When TCNT = GRB and GRB is functioning as output compare register When TCNT value is transferred to GRB by input capture signal and GRB is functioning as input capture register When 0 is written to IMFB after reading IMFB = 1
[Clearing condition] * 0 IMFA 0 R/W Input Capture/Compare Match Flag A [Setting conditions] * * When TCNT = GRA and GRA is functioning as output compare register When TCNT value is transferred to GRA by input capture signal and GRA is functioning as input capture register When 0 is written to IMFA after reading IMFA = 1
[Clearing condition] * Note: Bit 5 is not the UDF flag in TSR_0. It is a reserved bit. It is always read as 1.
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Section 14 Timer Z
14.3.12 Timer Interrupt Enable Register (TIER) TIER enables or disables interrupt requests for overflow or GR compare match/input capture. Timer Z has two TIER registers, one for each channel.
Bit 7 to 5 4 Bit Name OVIE Initial Value All 1 0 R/W R/W Description Reserved These bits are always read as 1. Overflow Interrupt Enable 0: Interrupt requests (OVI) by OVF or UDF flag are disabled 1: Interrupt requests (OVI) by OVF or UDF flag are enabled 3 IMIED 0 R/W Input Capture/Compare Match Interrupt Enable D 0: Interrupt requests (IMID) by IMFD flag are disabled 1: Interrupt requests (IMID) by IMFD flag are enabled 2 IMIEC 0 R/W Input Capture/Compare Match Interrupt Enable C 0: Interrupt requests (IMIC) by IMFC flag are disabled 1: Interrupt requests (IMIC) by IMFC flag are enabled 1 IMIEB 0 R/W Input Capture/Compare Match Interrupt Enable B 0: Interrupt requests (IMIB) by IMFB flag are disabled 1: Interrupt requests (IMIB) by IMFB flag are enabled 0 IMIEA 0 R/W Input Capture/Compare Match Interrupt Enable A 0: Interrupt requests (IMIA) by IMFA flag are disabled 1: Interrupt requests (IMIA) by IMFA flag are enabled
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Section 14 Timer Z
14.3.13 PWM Mode Output Level Control Register (POCR) POCR control the active level in PWM mode. Timer Z has two POCR registers, one for each channel.
Bit 7 to 3 2 Bit Name POLD Initial Value All 1 0 R/W R/W Description Reserved These bits are always read as 1. PWM Mode Output Level Control D 0: The output level of FTIOD is low-active 1: The output level of FTIOD is high-active 1 POLC 0 R/W PWM Mode Output Level Control C 0: The output level of FTIOC is low-active 1: The output level of FTIOC is high-active 0 POLB 0 R/W PWM Mode Output Level Control B 0: The output level of FTIOB is low-active 1: The output level of FTIOB is high-active
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Section 14 Timer Z
14.3.14 Interface with CPU 1. 16-bit register TCNT and GR are 16-bit registers. Reading/writing in a 16-bit unit is enabled but disabled in an 8-bit unit since the data bus with the CPU is 16-bit width. These registers must always be accessed in a 16-bit unit. Figure 14.5 shows an example of accessing the 16-bit registers.
Internal data bus H C P U L Bus interface Module data bus
TCNTH
TCNTL
Figure 14.5 Accessing Operation of 16-Bit Register (between CPU and TCNT (16 bits)) 2. 8-bit register Registers other than TCNT and GR are 8-bit registers that are connected internally with the CPU in an 8-bit width. Figure 14.6 shows an example of accessing the 8-bit registers.
Internal data bus H C P U L Bus interface Module data bus
TSTR
Figure 14.6 Accessing Operation of 8-Bit Register (between CPU and TSTR (8 bits))
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Section 14 Timer Z
14.4
14.4.1
Operation
Counter Operation
When one of bits STR0 and STR1 in TSTR is set to 1, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. Figure 14.7 shows an example of the counter operation setting procedure.
Operation selection
[1] [1]
Select counter clock
[2] Periodic counter Free-running counter [3]
Select counter clearing source
[2]
Select output compare register
[3] [4]
Set period
[4]
[5]
Select the counter clock with bits TPSC2 to TPSC0 in TCR. When an external clock is selected, select the external clock edge with bits CKEG1 and CKEG0 in TCR. For periodic counter operation, select the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. Designate the general register selected in [2] as an output compare register by means of TIOR. Set the periodic counter cycle in the general register selected in [2]. Set the STR bit in TSTR to 1 to start the counter operation.
Start count operation
[5]
Figure 14.7 Example of Counter Operation Setting Procedure
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Section 14 Timer Z
1. Free-running count operation and periodic count operation Immediately after a reset, the TCNT counters for channels 0 and 1 are all designated as freerunning counters. When the relevant bit in TSTR is set to 1, the corresponding TCNT counter starts an increment operation as a free-running counter. When TCNT overflows, the OVF flag in TSR is set to 1. If the value of the OVIE bit in the corresponding TIER is 1 at this point, timer Z requests an interrupt. After overflow, TCNT starts an increment operation again from H'0000. Figure 14.8 illustrates free-running counter operation.
TCNT value
H'FFFF
H'0000
Time
STR0, STR1
OVF
Figure 14.8 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The GR registers for setting the period are designated as output compare registers, and counter clearing by compare match is selected by means of bits CCLR1 and CCLR0 in TCR. After the settings have been made, TCNT starts an increment operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in GR, the IMFA, IMFB, IMFC, or IMFD flag in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding IMIEA, IMIEB, IMIEC, or IMIED bit in TIER is 1 at this point, the timer Z requests an interrupt. After a compare match, TCNT starts an increment operation again from H'0000.
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Section 14 Timer Z
Figure 14.9 illustrates periodic counter operation.
TCNT value
Counter cleared by GR compare match GR value
H'0000
Time
STR
IMF
Figure 14.9 Periodic Counter Operation 2. TCNT count timing A. Internal clock operation A system clock () or three types of clocks (/2, /4, or /8) that divides the system clock can be selected by bits TPSC2 to TPSC0 in TCR. Figure 14.10 illustrates this timing.
Internal clock
TCNT input
TCNT
N-1
N
N+1
Figure 14.10 Count Timing at Internal Clock Operation
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Section 14 Timer Z
B. External clock operation An external clock input pin (TCLK) can be selected by bits TPSC2 to TPSC0 in TCR, and a detection edge can be selected by bits CKEG1 and CKEG0. To detect an external clock, the rising edge, falling edge, or both edges can be selected. The pulse width of the external clock needs two or more system clocks. Note that an external clock does not operate correctly with the lower pulse width. Figure 14.11 illustrates the detection timing of the rising and falling edges.
External clock input pin TCNT input
TCNT
N-1
N
N+1
Figure 14.11 Count Timing at External Clock Operation (Both Edges Detected)
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Section 14 Timer Z
14.4.2
Waveform Output by Compare Match
Timer Z can perform 0, 1, or toggle output from the corresponding FTIOA, FTIOB, FTIOC, or FTIOD output pin using compare match A, B, C, or D. Figure 14.12 shows an example of the setting procedure for waveform output by compare match.
Output selection [1] Select waveform output mode [1] Select 0 output, 1 output, or toggle output as a compare much output, by means of TIOR. The initial values set in TOCR are output unit the first compare match occurs. Set the timing for compare match generation in GRA/GRB/GRC/GRD. Enable or disable the timer output by TOER. Set the STR bit in TSTR to 1 to start the TCNT count operation.
Set output timing
[2]
[2] [3] [4]
Enable waveform output
[3]
Start count operation
[4]

Figure 14.12 Example of Setting Procedure for Waveform Output by Compare Match
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Section 14 Timer Z
1. Examples of waveform output operation Figure 14.13 shows an example of 0 output/1 output. In this example, TCNT has been designated as a free-running counter, and settings have been made such that 0 is output by compare match A, and 1 is output by compare match B. When the set level and the pin level coincide, the pin level does not change.
TCNT value
H'FFFF
H'0000
Time
FTIOB
No change
No change
FTIOA
No change
No change
Figure 14.13 Example of 0 Output/1 Output Operation Figure 14.14 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B.
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Section 14 Timer Z
TCNT value GRB
GRA
H'0000
Time
FTIOB
Toggle output
FTIOA
Toggle output
Figure 14.14 Example of Toggle Output Operation 2. Output compare timing The compare match signal is generated in the last state in which TCNT and GR match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD). When TCNT matches GR, the compare match signal is generated only after the next TCNT input clock pulse is input. Figure 14.15 shows an example of the output compare timing.
TCNT input
TCNT
N
N+1
GR Compare match signal
N
FTIOA to FTIOD
Figure 14.15 Output Compare Timing
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Section 14 Timer Z
14.4.3
Input Capture Function
The TCNT value can be transferred to GR on detection of the input edge of the input capture/output compare pin (FTIOA, FTIOB, FTIOC, or FTIOD). Rising edge, falling edge, or both edges can be selected as the detected edge. When the input capture function is used, the pulse width or period can be measured. Figure 14.16 shows an example of the input capture operation setting procedure.
Input selection
[1]
Select input edge of input capture
[1] [2] [2]
Designate GR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input edge of the input capture signal. Set the STR bit in TSTR to 1 to start the TCNT counter operation.
Start counter operation
Figure 14.16 Example of Input Capture Operation Setting Procedure
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Section 14 Timer Z
1. Example of input capture operation Figure 14.17 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the FTIOA pin input capture input edge, the falling edge has been selected as the FTIOB pin input capture input edge, and counter clearing by GRB input capture has been designated for TCNT.
Counter cleared by FTIOB input (falling edge)
TCNT value H'0180 H'0160
H'0005 H'0000 Time
FTIOB
FTIOA
GRA
H'0005
H'0160
GRB
H'0180
Figure 14.17 Example of Input Capture Operation
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Section 14 Timer Z
2. Input capture signal timing Input capture on the rising edge, falling edge, or both edges can be selected through settings in TIOR. Figure 14.18 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least two system clock () cycles.
Input capture input
Input capture signal
TCNT
N
GR
N
Figure 14.18 Input Capture Signal Timing
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Section 14 Timer Z
14.4.4
Synchronous Operation
In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables GR to be increased with respect to a single time base. Figure 14.19 shows an example of the synchronous operation setting procedure.
Synchronous operation selection
Set synchronous operation
[1]
Synchronous presetting
Synchronous clearing
Set TCNT
[2]
Clearing source generation channel?
Yes
No
Select counter clearing source Start counter operation
[3]
Select counter clearing source Start counter operation
[4]
[5]
[5]



[1] Set the SYNC bits in TMDR to 1. [2] When a value is written to either of the TCNT counters, the same value is simultaneously written to the other TCNT counter. [3] Set bits CCLR1 and CCLR0 in TCR to specify counter clearing by compare match/input capture. [4] Set bits CCLR1 and CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set the STR bit in TSTR to 1 to start the count operation.
Figure 14.19 Example of Synchronous Operation Setting Procedure
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Section 14 Timer Z
Figure 14.20 shows an example of synchronous operation. In this example, synchronous operation has been selected, FTIOB0 and FTIOB1 have been designated for PWM mode, GRA_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 counter clearing source. In addition, the same input clock has been set as the counter input clock for channel 0 and channel 1. Two-phase PWM waveforms are output from pins FTIOB0 and FTIOB1. At this time, synchronous presetting and synchronous operation by GRA_0 compare match are performed by TCNT counters. For details on PWM mode, see section 14.4.5, PWM Mode.
TCNT values GRA_0 GRA_1 GRB_0 GRB_1 H'0000 Time
Synchronous clearing by GRA_0 compare match
FTIOB0
FTIOB1
Figure 14.20 Example of Synchronous Operation 14.4.5 PWM Mode
In PWM mode, PWM waveforms are output from the FTIOB, FTIOC, and FTIOD output pins with GRA as a cycle register and GRB, GRC, and GRD as duty registers. The initial output level of the corresponding pin depends on the setting values of TOCR and POCR. Table 14.3 shows an example of the initial output level of the FTIOB0 pin. The output level is determined by the POLB to POLD bits corresponding to POCR. When POLB is 0, the FTIOB output pin is set to 0 by compare match B and set to 1 by compare match A. When POLB is 1, the FTIOB output pin is set to 1 by compare match B and cleared to 0 by compare match A. In PWM mode, maximum 6-phase PWM outputs are possible.
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Section 14 Timer Z
Figure 14.21 shows an example of the PWM mode setting procedure. Table 14.3 Initial Output Level of FTIOB0 Pin
TOB0 0 0 1 1 POLB 0 1 0 1 Initial Output Level 1 0 0 1
PWM mode [1] Select counter clock [2] Select counter clearing source [3] [2] [3] [4] Set initial output level [4] [5] Select output level [5] [6] [7] [8] [1] Select the counter clock with bits TPSC2 to TOSC0 in TCR. When an external clock is selected, select the external clock edge with bits CKEG1 and CKEG0 in TCR. Use bits CCLR1 and CCLR0 in TCR to select the counter clearing source. Select the PWM mode with bits PWMB0 to PWMD0 and PWMB1 to PWMD1 in TPMR. Set the initial output value with bits TOB0 to TOD0 and TOB1 to TOD1 in TOCR. Set the output level with bits POLB to POLD in POCR. Set the cycle in GRA, and set the duty in the other GR. Enable or disable the timer output by TOER. Set the STR bit in TSTR to 1 and start the counter operation.
Set PWM mode
Set GR
[6]
Enable waveform output
[7]
Start counter operation
[8]

Figure 14.21 Example of PWM Mode Setting Procedure
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Section 14 Timer Z
Figure 14.22 shows an example of operation in PWM mode. The output signals go to 1 and TCNT is reset at compare match A, and the output signals go to 0 at compare match B, C, and D (TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0).
TCNT value Counter cleared by GRA compare match GRA GRB GRC GRD H'0000 Time
FTIOB
FTIOC
FTIOD
Figure 14.22 Example of PWM Mode Operation (1)
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Section 14 Timer Z
Figure 14.23 shows another example of operation in PWM mode. The output signals go to 0 and TCNT is reset at compare match A, and the output signals go to 1 at compare match B, C, and D (TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 1).
TCNT value GRA GRB GRC GRD H'0000 Time
Counter cleared by GRA compare match
FTIOB
FTIOC
FTIOD
Figure 14.23 Example of PWM Mode Operation (2) Figures 14.24 (when TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0) and 14.25 (when TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 1) show examples of the output of PWM waveforms with duty cycles of 0% and 100% in PWM mode.
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Section 14 Timer Z
TCNT value
GRB rewritten
GRA
GRB
GRB rewritten
H'0000
Time
FTIOB
0% duty
TCNT value GRB rewritten GRA
When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. GRB rewritten GRB rewritten
GRB
H'0000
Time
FTIOB
100% duty
When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. TCNT value GRB rewritten GRA GRB rewritten
GRB rewritten GRB
H'0000
Time
FTIOB
100% duty
0% duty
Figure 14.24 Example of PWM Mode Operation (3)
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Section 14 Timer Z
TCNT value
GRB rewritten
GRA GRB rewritten GRB
H'0000
Time
FTIOB
0% duty
TCNT value GRB rewritten GRA
When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. GRB rewritten GRB rewritten
GRB
H'0000
Time
FTIOB
100% duty
TCNT value GRB rewritten GRA
When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. GRB rewritten
GRB rewritten GRB
H'0000
Time
FTIOB
100% duty
0% duty
Figure 14.25 Example of PWM Mode Operation (4)
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Section 14 Timer Z
14.4.6
Reset Synchronous PWM Mode
Three normal- and counter-phase PWM waveforms are output by combining channels 0 and 1 that one of changing points of waveforms will be common. In reset synchronous PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become PWM-output pins automatically. TCNT_0 performs an increment operation. Tables 14.4 and 14.5 show the PWM-output pins used and the register settings, respectively. Figure 14.26 shows the example of reset synchronous PWM mode setting procedure. Table 14.4 Output Pins in Reset Synchronous PWM Mode
Channel 0 0 0 1 1 1 1 Pin Name FTIOC0 FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 Input/Output Output Output Output Output Output Output Output Pin Function Toggle output in synchronous with PWM cycle PWM output 1 PWM output 1 (counter-phase waveform of PWM output 1) PWM output 2 PWM output 2 (counter-phase waveform of PWM output 2) PWM output 3 PWM output 3 (counter-phase waveform of PWM output 3)
Table 14.5 Register Settings in Reset Synchronous PWM Mode
Register TCNT_0 TCNT_1 GRA_0 GRB_0 GRA_1 GRB_1 Description Initial setting of H'0000 Not used (independently operates) Sets counter cycle of TCNT_0 Set a changing point of the PWM waveform output from pins FTIOB0 and FTIOD0. Set a changing point of the PWM waveform output from pins FTIOA1 and FTIOC1. Set a changing point of the PWM waveform output from pins FTIOB1 and FTIOD1.
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Section 14 Timer Z
Reset synchronous PWM mode
Stop counter operation
[1]
[1]
Select counter clock
[2]
[2]
Select counter clearing source
[3] [3]
Set reset synchronous PWM mode
[4] [4]
Initialize the output pin
[5] [5] [6] [7]
Set TCNT
[6]
Set GR
[7]
Enable waveform output
[8]
[8] [9]
Start counter operation
[9]
Clear bit STR0 in TSTR to 0 and stop the counter operation of TCNT_0. Set reset synchronous PWM mode after TCNT_0 stops. Select the counter clock with bits TPSC2 to TOSC0 in TCR. When an external clock is selected, select the external clock edge with bits CKEG1 and CKEG0 in TCR. Use bits CCLR1 and CCLR0 in TCR to select counter clearing source GRA_0. Select the reset synchronous PWM mode with bits CMD1 and CMD0 in TFCR. FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 become PWM output pins automatically. Set H'00 to TOCR. Set TCNT_0 as H'0000. TCNT1 does not need to be set. GRA_0 is a cycle register. Set a cycle for GRA_0. Set the changing point timing of the PWM output waveform for GRB_0, GRA_1, and GRB_1. Enable or disable the timer output by TOER. Set the STR bit in TSTR to 1 and start the counter operation.

Figure 14.26 Example of Reset Synchronous PWM Mode Setting Procedure
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Section 14 Timer Z
Figures 14.27 and 14.28 show examples of operation in reset synchronous PWM mode.
TCNT value Counter cleared by GRA compare match GRA_0 GRB_0 GRA_1 GRB_1 H'0000 Time
FTIOB0
FTIOD0 FTIOA1
FTIOC1 FTIOB1
FTIOD1
FTIOC0
Figure 14.27 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 1)
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Section 14 Timer Z
TCNT value Counter cleared by GRA compare match GRA_0 GRB_0 GRA_1 GRB_1 H'0000 Time
FTIOB0
FTIOD0
FTIOA1
FTIOC1
FTIOB1
FTIOD1
FTIOC0
Figure 14.28 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0) In reset synchronous PWM mode, TCNT_0 and TCNT_1 perform increment and independent operations, respectively. However, GRA_1 and GRB_1 are separated from TCNT_1. When a compare match occurs between TCNT_0 and GRA_0, a counter is cleared and an increment operation is restarted from H'0000. The PWM pin outputs 0 or 1 whenever a compare match between GRB_0, GRA_1, GRB_1 and TCNT_0 or counter clearing occur. For details on operations when reset synchronous PWM mode and buffer operation are simultaneously set, see section 14.4.8, Buffer Operation.
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Section 14 Timer Z
14.4.7
Complementary PWM Mode
Three PWM waveforms for non-overlapped normal and counter phases are output by combining channels 0 and 1. In complementary PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become PWM-output pins automatically. TCNT_0 and TCNT_1 perform an increment or decrement operation. Tables 14.6 and 14.7 show the output pins and register settings in complementary PWM mode, respectively. Figure 14.29 shows the example of complementary PWM mode setting procedure. Table 14.6 Output Pins in Complementary PWM Mode
Channel 0 0 0 1 1 1 1 Pin Name FTIOC0 FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 Input/Output Output Output Output Output Output Output Output Pin Function Toggle output in synchronous with PWM cycle PWM output 1 PWM output 1 (counter-phase waveform nonoverlapped with PWM output 1) PWM output 2 PWM output 2 (counter-phase waveform nonoverlapped with PWM output 2) PWM output 3 PWM output 3 (counter-phase waveform nonoverlapped with PWM output 3)
Table 14.7 Register Settings in Complementary PWM Mode
Register TCNT_0 TCNT_1 GRA_0 GRB_0 GRA_1 GRB_1 Description Initial setting of non-overlapped periods (non-overlapped periods are differences with TCNT_1) Initial setting of H'0000 Sets (upper limit value - 1) of TCNT_0 Set a changing point of the PWM waveform output from pins FTIOB0 and FTIOD0. Set a changing point of the PWM waveform output from pins FTIOA1 and FTIOC1. Set a changing point of the PWM waveform output from pins FTIOB1 and FTIOD1.
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Complementary PWM mode
[1]
Stop counter operation
[1] [2] [3]
Initialize output pin
[2]
Select counter clock
[3]
Set complementary PWM mode
[4] [4]
Initialize output pin
[5]
[5] [6] [7]
Set TCNT
[6] [7]
Set GR
Enable waveform output
[8]
Start counter operation
[9] [8] [9]

Clear bits STR0 and STR1 in TSTR to 0, and stop the counter operation of TCNT_0. Stop TCNT_0 and TCNT_1 and set complementary PWM mode. Write H'00 to TOCR. Use bits TPSC2 to TPSC0 in TCR to select the same counter clock for channels 0 and 1. When an external clock is selected, select the edge of the external clock by bits CKEG1 and CKEG0 in TCR. Do not use bits CCLR1 and CCLR0 in TCR to clear the counter. Use bits CMD1 and CMD0 in TFCR to set complementary PWM mode. FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 automatically become PWM output pins. Set H'00 to TOCR. TCNT_1 must be H'0000. Set a non-overlapped period to TCNT_0. GRA_0 is a cycle register. Set the cycle to GRA_0. Set the timing to change the PWM output waveform to GRB_0, GRA_1, and GRB_1. Note that the timing must be set within the range of compare match carried out for TCNT_0 and TCNT_1. For GR settings, see 3. Setting GR Value in Complementary PWM Mode in section 14.4.7, Complementary PWM Mode. Use TOER to enable or disable the timer output. Set the STR0 and STR1 bits in TSTR to 1 to start the count operation.
Note:
To re-enter complementary PWM mode, first, enter a mode other than the complementary PWM mode. After that, repeat the setting procedures from step [1]. For settings of waveform outputs with a duty cycle of 0% and 100%, see the settings shown in 2. Examples of Complementary PWM Mode Operation and 3. Setting GR Value in Complementary PWM Mode in section 14.4.7, Complementary PWM Mode.
Figure 14.29 Example of Complementary PWM Mode Setting Procedure
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1.
Canceling Procedure of Complementary PWM Mode: Figure 14.30 shows the complementary PWM mode canceling procedure.
Complementary PWM mode [1] Stop counter operation [1] [2] Cancel complementary PWM mode [2] Clear bit CMD1 in TFCR to 0, and set channels 0 and 1 to normal operation. After setting channels 0 and 1 to normal operation, clear bits STR0 and STR1 in TSTR to 0 and stop TCNT0 and TCNT1.

Figure 14.30 Canceling Procedure of Complementary PWM Mode
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2. Examples of Complementary PWM Mode Operation: Figure 14.31 shows an example of complementary PWM mode operation. In complementary PWM mode, TCNT_0 and TCNT_1 perform an increment or decrement operation. When TCNT_0 and GRA_0 are compared and their contents match, the counter is decremented, and when TCNT_1 underflows, the counter is incremented. In GRA_0, GRA_1, and GRB_1, compare match is carried out in the order of TCNT_0 TCNT_1 TCNT_1 TCNT_0 and PWM waveform is output, during one cycle of an up/down counter. In this mode, the initial setting will be TCNT_0 > TCNT_1.
TCNT values GRA_0 GRB_0 GRA_1 GRB_1 H'0000
TCNT_0 and GRA_0 are compared and their contents match
Time
FTIOB0
FTIOD0
FTIOA1
FTIOC1
FTIOB1
FTIOD1
FTIOC0
Figure 14.31 Example of Complementary PWM Mode Operation (1)
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Figure 14.32 (1) and (2) show examples of PWM waveform output with 0% duty and 100% duty in complementary PWM mode (for one phase). * TPSC2 = TPSC1 = TPSC0 = 0 Set GRB_0 to H'0000 or a value equal to or more than GRA_0. The waveform with a duty cycle of 0% and 100% can be output. When buffer operation is used together, the duty cycles can easily be changed, including the above settings, during operation. For details on buffer operation, see section 14.4.8, Buffer Operation. * Other than TPSC2 = TPSC1 = TPSC0 = 0 Set GRB_0 to satisfy the following expression: GRA_0 + 1 < GRB_0 < H'FFFF. The waveform with a duty cycle of 0% and 100% can be output. For details on 0%- and 100%-duty cycle waveform output, see 3. C., Outputting a waveform with a duty cycle of 0% and 100% in section 14.4.7, Complementary PWM Mode.
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TCNT values
GRA0
GRB0
H'0000
Time
FTIOB0
FTIOD0
0% duty (a) When duty is 0%
TCNT values
GRA0
GRB0
H'0000
Time
FTIOB0
FTIOD0 100% duty
(b) When duty is 100%
Figure 14.32 (1) Example of Complementary PWM Mode Operation (TPSC2 = TPSC1 = TPSC0 = 0) (2)
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TCNT values
GRA0
GRB0
H'0000
Time
FTIOB0
FTIOD0
0% duty (a) When duty is 0%
TCNT values
GRA0
GRB0
H'0000
Time
FTIOB0
FTIOD0 100% duty
(b) When duty is 100%
Figure 14.32 (2) Example of Complementary PWM Mode Operation (TPSC2 = TPSC1 = TPSC0 0) (3)
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In complementary PWM mode, when the counter switches from up-counter to down-counter or vice versa, TCNT_0 and TCNT_1 overshoots or undershoots, respectively. In this case, the conditions to set the IMFA flag in channel 0 and the UDF flag in channel 1 differ from usual settings. Also, the transfer conditions in buffer operation differ from usual settings. Such timings are shown in figures 14.33 and 14.34.
TCNT
N-1
N
N+1
N
N-1
GRA_0
N
IMFA Set to 1 Flag is not set Buffer transfer signal
GR Transferred to buffer Not transferred to buffer
Figure 14.33 Timing of Overshooting
TCNT
H'0001
H'0000
H'FFFF
H'0000
H'0001
Flag is not set UDF Set to 1 Buffer transfer signal
GR Transferred to buffer Not transferred to buffer
Figure 14.34 Timing of Undershooting
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When the counter is incremented or decremented, the IMFA flag of channel 0 is set to 1, and when the register is underflowed, the UDF flag of channel 0 is set to 1. After buffer operation has been designated for BR, BR is transferred to GR when the counter is incremented by compare match A0 or when TCNT_1 is underflowed. If the or /2 clock is selected by TPSC2 to TPSC0 bits, the OVF flag is not set to 1 at the timing that the counter value changes from H'FFFF to H'0000. If the /4 or /8 clock is selected by TPSC2 to TPSC0 bits, the OVF flag is set to 1. 3. Setting GR Value in Complementary PWM Mode: To set the general register (GR) or modify GR during operation in complementary PWM mode, refer to the following notes. A. Initial value a. When other than TPSC2 = TPSC1 = TPSC0 = 0, the GRA_0 value must be equal to H'FFFC or less. When TPSC2 = TPSC1 = TPSC0 = 0, the GRA_0 value can be set to H'FFFF or less. b. H'0000 to T - 1 (T: Initial value of TCNT0) must not be set for the initial value. c. GRA_0 - (T - 1) or more must not be set for the initial value. d. When using buffer operation, the same values must be set in the buffer registers and corresponding general registers. B. Modifying the setting value a. Writing to GR directly must be performed while the TCNT_1 and TCNT_0 values should satisfy the following expression: H'0000 TCNT_1 < previous GR value, and previous GR value < TCNT_0 GRA_0. Otherwise, a waveform is not output correctly. For details on outputting a waveform with a duty cycle of 0% and 100%, see C., Outputting a waveform with a duty cycle of 0% and 100%. b. Do not write the following values to GR directly. When writing the values, a waveform is not output correctly. H'0000 GR T - 1 and GRA_0 - (T - 1) GR < GRA_0 when TPSC2 = TPSC1 = TPSC0 = 0 H'0000 < GR T - 1 and GRA_0 - (T - 1) GR < GRA_0 + 1 when TPSC2 = TPSC1 = TPSC0 = 0 c. Do not change settings of GRA_0 during operation. C. Outputting a waveform with a duty cycle of 0% and 100% a. Buffer operation is not used and TPSC2 = TPSC1 = TPSC0 = 0 Write H'0000 or a value equal to or more than the GRA_0 value to GR directly at the timing shown below. * To output a 0%-duty cycle waveform, write a value equal to or more than the GRA_0 value while H'0000 TCNT_1 < previous GR value
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* To output a 100%-duty cycle waveform, write H'0000 while previous GR value< TCNT_0 GRA_0 To change duty cycles while a waveform with a duty cycle of 0% or 100% is being output, make sure the following procedure. To change duty cycles while a 0%-duty cycle waveform is being output, write to GR while H'0000 TCNT_1 < previous GR value To change duty cycles while a 100%-duty cycle waveform is being output, write to GR while previous GR value< TCNT_0 GRA_0 Note that changing from a 0%-duty cycle waveform to a 100%-duty cycle waveform and vice versa is not possible. Buffer operation is used and TPSC2 = TPSC1 = TPSC0 = 0 Write H'0000 or a value equal to or more than the GRA_0 value to the buffer register. To output a 0%-duty cycle waveform, write a value equal to or more than the GRA_0 value to the buffer register To output a 100%-duty cycle waveform, write H'0000 to the buffer register For details on buffer operation, see section 14.4.8, Buffer Operation. Buffer operation is not used and other than TPSC2 = TPSC1 = TPSC0 = 0 Write a value which satisfies GRA_0 + 1 < GR < H'FFFF to GR directly at the timing shown below. To output a 0%-duty cycle waveform, write the value while H'0000 TCNT_1 < previous GR value To output a 100%-duty cycle waveform, write the value while previous GR value< TCNT_0 GRA_0
* *
b. * * c.
* *
To change duty cycles while a waveform with a duty cycle of 0% and 100% is being output, the following procedure must be followed. * To change duty cycles while a 0%-duty cycle waveform is being output, write to GR while H'0000 TCNT_1 < previous GR value * To change duty cycles while a 100%-duty cycle waveform is being output, write to GR while previous GR value< TCNT_0 GRA_0 Note that changing from a 0%-duty cycle waveform to a 100%-duty cycle waveform and vice versa is not possible.
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d. Buffer operation is used and other than TPSC2 = TPSC1 = TPSC0 = 0 Write a value which satisfies GRA_0 + 1 < GR < H'FFFF to the buffer register. A waveform with a duty cycle of 0% can be output. However, a waveform with a duty cycle of 100% cannot be output using the buffer operation. Also, the buffer operation cannot be used to change duty cycles while a waveform with a duty cycle of 100% is being output. For details on buffer operation, see section 14.4.8, Buffer Operation. 14.4.8 Buffer Operation
Buffer operation differs depending on whether GR has been designated for an input capture register or an output compare register, or in reset synchronous PWM mode or complementary PWM mode. Table 14.8 shows the register combinations used in buffer operation. Table 14.8 Register Combinations in Buffer Operation
General Register GRA GRB Buffer Register GRC GRD
1. When GR is an output compare register When a compare match occurs, the value in the buffer register of the corresponding channel is transferred to the general register. This operation is illustrated in figure 14.35.
Compare match signal
Buffer register
General register
Comparator
TCNT
Figure 14.35 Compare Match Buffer Operation
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2. When GR is an input capture register When an input capture occurs, the value in TCNT is transferred to the general register and the value previously stored in the general register is transferred to the buffer register. This operation is illustrated in figure 14.36.
Input capture signal
Buffer register
General register
TCNT
Figure 14.36 Input Capture Buffer Operation 3. Complementary PWM Mode When the counter switches from counting up to counting down or vice versa, the value of the buffer register is transferred to the general register. Here, the value of the buffer register is transferred to the general register in the following timing: A. When TCNT_0 and GRA_0 are compared and their contents match B. When TCNT_1 underflows 4. Reset Synchronous PWM Mode The value of the buffer register is transferred from compare match A0 to the general register. 5. Example of Buffer Operation Setting Procedure Figure 14.37 shows an example of the buffer operation setting procedure.
Buffer operation
[1] [1] [2] [3]
Select GR function
Set buffer operation
[2]
Designate GR as an input capture register or output compare register by means of TIOR. Designate GR for buffer operation with bits BFD1, BFC1, BFD0, or BFC0 in TMDR. Set the STR bit in TSTR to 1 to start the count operation of TCNT.
Start count operation
[3]

Figure 14.37 Example of Buffer Operation Setting Procedure
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Section 14 Timer Z
6. Examples of Buffer Operation Figure 14.38 shows an operation example in which GRA has been designated as an output compare register, and buffer operation has been designated for GRA and GRC. This is an example of TCNT operating as a periodic counter cleared by compare match B. Pins FTIOA and FTIOB are set for toggle output by compare match A and B. As buffer operation has been set, when compare match A occurs, the FTIOA pin performs toggle outputs and the value in buffer register is simultaneously transferred to the general register. This operation is repeated each time that compare match A occurs. The timing to transfer data is shown in figure 14.39.
TCNT value GRB
Counter is cleared by GBR compare match
H'0250 H'0200 H'0100 H'0000 Time
GRC
H'0200
H'0100
H'0200
GRA
H'0250
H'0200
H'0100
H'0200
FTIOB
FTIOA
Compare match A
Figure 14.38 Example of Buffer Operation (1) (Buffer Operation for Output Compare Register)
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Section 14 Timer Z
TCNT Compare match signal Buffer transfer signal GRC
n
n+1
N
GRA
n
N
Figure 14.39 Example of Compare Match Timing for Buffer Operation Figure 14.40 shows an operation example in which GRA has been designated as an input capture register, and buffer operation has been designated for GRA and GRC. Counter clearing by input capture B has been set for TCNT, and falling edges have been selected as the FIOCB pin input capture input edge. And both rising and falling edges have been selected as the FIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in GRA upon the occurrence of input capture A, the value previously stored in GRA is simultaneously transferred to GRC. The transfer timing is shown in figure 14.41.
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TCNT value H'0180 H'0160
Counter is cleared by the input capture B
H'0005 H'0000 Time
FTIOB
FTIOA
GRA
H'0005
H'0160
GRC
H'0005
H'0160
GRB
H'0180
Input capture A
Figure 14.40 Example of Buffer Operation (2) (Buffer Operation for Input Capture Register)
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Section 14 Timer Z
FTIO pin Input capture signal
TCNT
n
n+1
N
N+1
GRA
M
n
n
N
GRC
m
M
M
n
Figure 14.41 Input Capture Timing of Buffer Operation
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Section 14 Timer Z
Figures 14.42 and 14.43 show the operation examples when buffer operation has been designated for GRB_0 and GRD_0 in complementary PWM mode. These are examples when a PWM waveform of 0% duty is created by using the buffer operation and performing GRD_0 GRA_0. Data is transferred from GRD_0 to GRB_0 according to the settings of CMD_0 and CMD_1 when TCNT_0 and GRA_0 are compared and their contents match or when TCNT_1 underflows. However, when GRD_0 GRA_0, data is transferred from GRD_0 to GRB_0 when TCNT_1 underflows regardless of the setting of CMD_0 and CMD_1. When GRD_0 = H'0000, data is transferred from GRD_0 to GRB_0 when TCNT_0 and GRA_0 are compared and their contents match regardless of the settings of CMD_0 and CMD_1.
TCNT values TCNT_0 GRA_0 TCNT_1 H'0999
GRB_0 (When restored, data will be transferred to the saved location regardless of the CMD1 and CMD0 values)
H'0000
Time
GRD_0 H'0999
H'1FFF
H'0999
GRB_0 H'0999
H'0999
H'1FFF
H'0999
FTIOB0
FTIOD0
Figure 14.42 Buffer Operation (3) (Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1)
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Section 14 Timer Z
TCNT values TCNT_0 GRA_0 TCNT_1 H'0999
GRB_0 (When restored, data will be transferred to the saved location regardless of the CMD1 and CMD0 values)
H'0000 GRB_0 GRD_0 H'0999 H'0000 H'0999
Time
GRB_0 H'0999
H'0000
H'0999
FTIOC0
FTIOD0
Figure 14.43 Buffer Operation (4) (Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1)
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Section 14 Timer Z
14.4.9
Timer Z Output Timing
The outputs of channels 0 and 1 can be disabled or inverted by the settings of TOER and TOCR and the external level. 1. Output Disable/Enable Timing of Timer Z by TOER: Setting the master enable bit in TOER to 1 disables the output of timer Z. By setting the PCR and PDR of the corresponding I/O port beforehand, any value can be output. Figure 14.44 shows the timing to enable or disable the output of timer Z by TOER.
T1 T2
Address bus
TOER address
TOER
Timer Z output pin
Timer output Timer Z output
I/O port I/O port
Figure 14.44 Example of Output Disable Timing of Timer Z by Writing to TOER
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Section 14 Timer Z
2. Output Disable Timing of Timer Z by External Trigger: When P54/WKP4 is set as a WKP4 input pin, and low level is input to WKP4, the master enable bit in TOER is set to 1 and the output of timer Z will be disabled.
WKP4
TOER
N
H'FF
Timer Z output pin
Timer Z output
I/O port
Timer Z output
I/O port
Figure 14.45 Example of Output Disable Timing of Timer Z by External Trigger 3. Output Inverse Timing by TFCR: The output level can be inverted by inverting the OLS1 and OLS0 bits in TFCR in reset synchronous PWM mode or complementary PWM mode. Figure 14.46 shows the timing.
T1 T2
Address bus
TOER address
TFCR Timer Z output pin Inverted
Figure 14.46 Example of Output Inverse Timing of Timer Z by Writing to TFCR
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Section 14 Timer Z
4. Output Inverse Timing by POCR: The output level can be inverted by inverting the POLD, POLC, and POLB bits in POCR in PWM mode. Figure 14.47 shows the timing.
T1 Address bus POCR address T2
TFCR Timer Z output pin Inverted
Figure 14.47 Example of Output Inverse Timing of Timer Z by Writing to POCR
14.5
Interrupts
There are three kinds of timer Z interrupt sources; input capture/compare match, overflow, and underflow. An interrupt is requested when the corresponding interrupt request flag is set to 1 while the corresponding interrupt enable bit is set to 1. 14.5.1 1. Status Flag Set Timing
IMF Flag Set Timing: The IMF flag is set to 1 by the compare match signal that is generated when the GR matches with the TCNT. The compare match signal is generated at the last state of matching (timing to update the counter value when the GR and TCNT match). Therefore, when the TCNT and GR matches, the compare match signal will not be generated until the TCNT input clock is generated. Figure 14.48 shows the timing to set the IMF flag.
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Section 14 Timer Z
TCNT input clock
TCNT
N
N+1
GR Compare match signal IMF ITMZ
N
Figure 14.48 IMF Flag Set Timing when Compare Match Occurs 2. IMF Flag Set Timing at Input Capture: When an input capture signal is generated, the IMF flag is set to 1 and the value of TCNT is simultaneously transferred to corresponding GR. Figure 14.49 shows the timing.
Input capture signal
IMF
TCNT
N
GR
N
ITMZ
Figure 14.49 IMF Flag Set Timing at Input Capture
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Section 14 Timer Z
3. Overflow Flag (OVF) Set Timing: The overflow flag is set to 1 when the TCNT overflows. Figure 14.50 shows the timing.
TCNT Overflow signal H'FFFF H'0000
OVF ITMZ
Figure 14.50 OVF Flag Set Timing 14.5.2 Status Flag Clearing Timing
The status flag can be cleared by writing 0 after reading 1 from the CPU. Figure 14.51 shows the timing in this case.
Address WTSR (internal write signal) TSR address
IMF, OVF
ITMZ
Figure 14.51 Status Flag Clearing Timing
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Section 14 Timer Z
14.6
Usage Notes
1. Contention between TCNT Write and Clear Operations: If a counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing has priority and the TCNT write is not performed. Figure 14.52 shows the timing in this case.
TCNT write cycle T1 T2
TCNT address WTCNT (internal write signal) Counter clear signal
TCNT
N
H'0000 Clearing has priority.
Figure 14.52 Contention between TCNT Write and Clear Operations 2. Contention between TCNT Write and Increment Operations: If incrementation is done in T2 state of a TCNT write cycle, TCNT writing has priority. Figure 14.53 shows the timing in this case.
TCNT write cycle T1 T2 TCNT address WTCNT (internal write signal) TCNT input clock
TCNT
N TCNT write data
M
Figure 14.53 Contention between TCNT Write and Increment Operations
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Section 14 Timer Z
3. Contention between GR Write and Compare Match: If a compare match occurs in the T2 state of a GR write cycle, GR write has priority and the compare match signal is disabled. Figure 14.54 shows the timing in this case.
GR write cycle T1 T2
GR address WGR (internal write signal) TCNT
N
N+1
GR N GR write data Compare match signal Disabled M
Figure 14.54 Contention between GR Write and Compare Match
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Section 14 Timer Z
4. Contention between TCNT Write and Overflow/Underflow: If overflow/underflow occurs in the T2 state of a TCNT write cycle, TCNT write has priority without an increment operation. At this time, the OVF flag is set to 1. Figure 14.55 shows the timing in this case.
TCNT write cycle T1 T2
TCNT address WTCNT (internal write signal) TCNT input clock
Overflow signal
TCNT
H'FFFF TCNT write data
M
OVF
Figure 14.55 Contention between TCNT Write and Overflow
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Section 14 Timer Z
5. Contention between GR Read and Input Capture: If an input capture signal is generated in the T1 state of a GR read cycle, the data that is read will be transferred before input capture transfer. Figure 14.56 shows the timing in this case.
GR read cycle T1 T2
GR address Internal read signal Input capture signal
GR Internal data bus
X
M
X
Figure 14.56 Contention between GR Read and Input Capture
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Section 14 Timer Z
6. Contention between Count Clearing and Increment Operations by Input Capture: If an input capture and increment signals are simultaneously generated, count clearing by the input capture operation has priority without an increment operation. The TCNT contents before clearing counter are transferred to GR. Figure 14.57 shows the timing in this case.
Input capture signal Counter clear signal TCNT input clock
TCNT
N
H'0000
GR
N Clearing has priority.
Figure 14.57 Contention between Count Clearing and Increment Operations by Input Capture
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Section 14 Timer Z
7. Contention between GR Write and Input Capture: If an input capture signal is generated in the T2 state of a GR write cycle, the input capture operation has priority and the write to GR is not performed. Figure 14.58 shows the timing in this case.
GR write cycle T1 T2
Address bus WGR (internal write signal) Input capture signal TCNT N
GR address
GR
M GR write data
Figure 14.58 Contention between GR Write and Input Capture 8. Notes on Setting Reset Synchronous PWM Mode/Complementary PWM Mode: When bits CMD1 and CMD0 in TFCR are set, note the following: A. Write bits CMD1 and CMD0 while TCNT_1 and TCNT_0 are halted. B. Changing the settings of reset synchronous PWM mode to complementary PWM mode or vice versa is disabled. Set reset synchronous PWM mode or complementary PWM mode after the normal operation (bits CMD1 and CMD0 are cleared to 0) has been set. 9. Notes on Writing to the TOA0 to TOD0 Bits and the TOA1 to TOD1 Bits in TOCR: The TOA0 to TOD0 bits and the TOA1 to TOD1 bits in TOCR decide the value of the FTIO pin, which is output until the first compare match occurs. Once a compare match occurs and this compare match changes the values of FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 output, the values of the FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pin output and the values read from the TOA0 to TOD0 and TOA1 to TOD1 bits may differ. Moreover, when the writing to TOCR and the generation of the compare match A0 to D0 and A1 to D1 occur at the same timing, the writing to TOCR has the priority. Thus, output change due to the compare match is not reflected to the FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pins. Therefore, when bit manipulation instruction is used to write to TOCR, the values of the FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pin output may result in an unexpected result. When TOCR is to be written to while compare match is operating, stop the counter once before accessing to
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Section 14 Timer Z
TOCR, read the port 6 state to reflect the values of FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 output, to TOA0 to TOD0 and TOA1 to TOD1, and then restart the counter. Figure 14.59 shows an example when the compare match and the bit manipulation instruction to TOCR occur at the same timing.
TOCR has been set to H'06. Compare match B0 and compare match C0 are used. The FTIOB0 pin is in the 1 output state, and is set to the toggle output or the 0 output by compare match B0. When BCLR#2, @TOCR is executed to clear the TOC0 bit (the FTIOC0 signal is low) and compare match B0 occurs at the same timing as shown below, the H'02 writing to TOCR has priority and compare match B0 does not drive the FTIOB0 signal low; the FTIOB0 signal remains high. Bit TOCR Set value 7 TOD1 0 6 TOC1 0 5 TOB1 0 4 TOA1 0 3 TOD0 0 2 TOC0 1 1 TOB0 1 0 TOA0 0
BCLR#2, @TOCR (1) TOCR read operation: Read H'06 (2) Modify operation: Modify H'06 to H'02 (3) Write operation to TOCR: Write H'02
TOCR write signal Compare match signal B0
FTIOB0 pin
Expected output Remains high because the 1 writing to TOB has priority
Figure 14.59 When Compare Match and Bit Manipulation Instruction to TOCR Occur at the Same Timing
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Section 14 Timer Z
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Section 15 Watchdog Timer
Section 15 Watchdog Timer
The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. The block diagram of the watchdog timer is shown in figure 15.1.
Internal oscillator
CLK
TCSRWD
PSS
TCWD
TMWD [Legend] TCSRWD: TCWD: PSS: TMWD:
Timer control/status register WD Timer counter WD Prescaler S Timer mode register WD
Internal reset signal
Figure 15.1 Block Diagram of Watchdog Timer
15.1
Features
* Selectable from nine counter input clocks. Eight clock sources (/64, /128, /256, /512, /1024, /2048, /4096, and /8192) or the internal oscillator can be selected as the timer-counter clock. When the internal oscillator is selected, it can operate as the watchdog timer in any operating mode. * Reset signal generated on counter overflow An overflow period of 1 to 256 times the selected clock can be set.
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Internal data bus
Section 15 Watchdog Timer
15.2
Register Descriptions
The watchdog timer has the following registers. * Timer control/status register WD (TCSRWD) * Timer counter WD (TCWD) * Timer mode register WD (TMWD) 15.2.1 Timer Control/Status Register WD (TCSRWD)
TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the watchdog timer operation and indicates the operating state. TCSRWD must be rewritten by using the MOV instruction. The bit manipulation instruction cannot be used to change the setting value.
Bit 7 Bit Name B6WI Initial Value 1 R/W R/W Description Bit 6 Write Inhibit The TCWE bit can be written only when the write value of the B6WI bit is 0. This bit is always read as 1. 6 TCWE 0 R/W Timer Counter WD Write Enable TCWD can be written when the TCWE bit is set to 1. When writing data to this bit, the value for bit 7 must be 0. 5 B4WI 1 R/W Bit 4 Write Inhibit The TCSRWE bit can be written only when the write value of the B4WI bit is 0. This bit is always read as 1. 4 TCSRWE 0 R/W Timer Control/Status Register WD Write Enable The WDON and WRST bits can be written when the TCSRWE bit is set to 1. When writing data to this bit, the value for bit 5 must be 0. 3 B2WI 1 R/W Bit 2 Write Inhibit This bit can be written to the WDON bit only when the write value of the B2WI bit is 0. This bit is always read as 1.
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Section 15 Watchdog Timer
Bit 2
Bit Name WDON
Initial Value 0
R/W R/W
Description Watchdog Timer On TCWD starts counting up when WDON is set to 1 and halts when WDON is cleared to 0. [Setting condition] When 1 is written to the WDON bit while writing 0 to the B2WI bit when the TCSRWE bit=1 [Clearing conditions] * * Reset by RES pin When 0 is written to the WDON bit while writing 0 to the B2WI when the TCSRWE bit=1
1
B0WI
1
R/W
Bit 0 Write Inhibit This bit can be written to the WRST bit only when the write value of the B0WI bit is 0. This bit is always read as 1.
0
WRST
0
R/W
Watchdog Timer Reset [Setting condition] When TCWD overflows and an internal reset signal is generated [Clearing conditions] * * Reset by RES pin When 0 is written to the WRST bit while writing 0 to the B0WI bit when the TCSRWE bit=1
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Section 15 Watchdog Timer
15.2.2
Timer Counter WD (TCWD)
TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the internal reset signal is generated and the WRST bit in TCSRWD is set to 1. TCWD is initialized to H'00. 15.2.3 Timer Mode Register WD (TMWD)
TMWD selects the input clock.
Bit 7 to 4 3 2 1 0 Bit Name CKS3 CKS2 CKS1 CKS0 Initial Value All 1 1 1 1 1 R/W R/W R/W R/W R/W Description Reserved These bits are always read as 1. Clock Select 3 to 0 Select the clock to be input to TCWD. 1000: Internal clock: counts on /64 1001: Internal clock: counts on /128 1010: Internal clock: counts on /256 1011: Internal clock: counts on /512 1100: Internal clock: counts on /1024 1101: Internal clock: counts on /2048 1110: Internal clock: counts on /4096 1111: Internal clock: counts on /8192 0xxx: Internal oscillator For the internal oscillator overflow periods, see section 23, Electrical Characteristics. [Legend] x: Don't care.
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Section 15 Watchdog Timer
15.3
Operation
The watchdog timer is provided with an 8-bit counter. If 1 is written to WDON while writing 0 to B2WI when the TCSRWE bit in TCSRWD is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write accesses to TCSRWD are required.) When a clock pulse is input after the TCWD count value has reached H'FF, the watchdog timer overflows and an internal reset signal is generated. The internal reset signal is output for a period of 256 osc clock cycles. TCWD is a writable counter, and when a value is set in TCWD, the count-up starts from that value. An overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the TCWD set value. Figure 15.2 shows an example of watchdog timer operation.
Example: With 30ms overflow period when = 4 MHz 4 x 106 8192 x 30 x 10-3 = 14.6
Therefore, 256 - 15 = 241 (H'F1) is set in TCW. TCWD overflow
H'FF H'F1 TCWD count value
H'00 Start H'F1 written to TCWD Internal reset signal 256 osc clock cycles H'F1 written to TCWD Reset generated
Figure 15.2 Watchdog Timer Operation Example
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Section 15 Watchdog Timer
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Section 16 14-Bit PWM
Section 16 14-Bit PWM
The 14-bit PWM is a pulse division type PWM that can be used for electronic tuner control, etc. Figure 16.1 shows a block diagram of the 14-bit PWM.
16.1
Features
* Choice of two conversion periods A conversion period of 32768/ with a minimum modulation width of 2/, or a conversion period of 16384/ with a minimum modulation width of 1/, can be selected. * Pulse division method for less ripple
PWDRL PWDRU
/4 /2 [Legend] PWCR: PWDRL: PWDRU: PWM:
PWM waveform generator
Internal data bus
PWM
PWCR
PWM control register PWM data register L PWM data register U PWM output pin
Figure 16.1 Block Diagram of 14-Bit PWM
16.2
Input/Output Pin
Table 16.1 shows the 14-bit PWM pin configuration. Table 16.1 Pin Configuration
Name 14-bit PWM square-wave output Abbreviation I/O PWM Output Function 14-bit PWM square-wave output pin
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Section 16 14-Bit PWM
16.3
Register Descriptions
The 14-bit PWM has the following registers. * PWM control register (PWCR) * PWM data register U (PWDRU) * PWM data register L (PWDRL) 16.3.1 PWM Control Register (PWCR)
PWCR selects the conversion period.
Bit 7 6 5 4 3 2 1 0 Bit Name PWCR0 Initial Value 1 1 1 1 1 1 1 0 R/W R/W Description Reserved These bits are always read as 1, and cannot be modified.
Clock Select 0: The input clock is /2 (t = 2/) The conversion period is 16384/, with a minimum modulation width of 1/ 1: The input clock is /4 (t = 4/) The conversion period is 32768/, with a minimum modulation width of 2/
[Legend] t: Period of PWM clock input
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Section 16 14-Bit PWM
16.3.2
PWM Data Registers U, L (PWDRU, PWDRL)
PWDRU and PWDRL indicate high level width in one PWM waveform cycle. PWDRU and PWDRL are 14-bit write-only registers, with the upper 6 bits assigned to PWDRU and the lower 8 bits to PWDRL. When read, all bits are always read as 1. Both PWDRU and PWDRL are accessible only in bytes. Note that the operation is not guaranteed if word access is performed. When 14-bit data is written in PWDRU and PWDRL, the contents are latched in the PWM waveform generator and the PWM waveform generation data is updated. When writing the 14-bit data, the order is as follows: PWDRL to PWDRU. PWDRU and PWDRL are initialized to H'C000.
16.4
Operation
When using the 14-bit PWM, set the registers in this sequence: 1. Set the PWM bit in the port mode register 1 (PMR1) to set the P11/PWM pin to function as a PWM output pin. 2. Set the PWCR0 bit in PWCR to select a conversion period of either. 3. Set the output waveform data in PWDRU and PWDRL. Be sure to write byte data first to PWDRL and then to PWDRU. When the data is written in PWDRU, the contents of these registers are latched in the PWM waveform generator, and the PWM waveform generation data is updated in synchronization with internal signals. One conversion period consists of 64 pulses, as shown in figure 16.2. The total high-level width during this period (TH) corresponds to the data in PWDRU and PWDRL. This relation can be expressed as follows:
TH = (data value in PWDRU and PWDRL + 64) x t/2
where t is the period of PWM clock input: 2/ (bit PWCR0 = 0) or 4/ (bit PWCR0 = 1). If the data value in PWDRU and PWDRL is from H'FFC0 to H'FFFF, the PWM output stays high. When the data value is H'C000, TH is calculated as follows:
TH = 64 x t/2 = 32 t
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Section 16 14-Bit PWM
Conversion period t f1 t f2 t f63 t f64
t H1
t H2
t H3
t H63
t H64
T H = t H1 + t H2 + t H3 + ... + t H64 t f1 = t f2 = t f3 = ... = t f64
Figure 16.2 Waveform Output by 14-Bit PWM
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Section 17 Serial Communication Interface 3 (SCI3)
Section 17 Serial Communication Interface 3 (SCI3)
This LSI includes a serial communication interface 3 (SCI3), which has independent three channels. The SCI3 can handle both asynchronous and clocked synchronous serial communication. In asynchronous mode, serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). Table 17.1 shows the SCI3 channel configuration and figure 17.1 shows a block diagram of the SCI3. Since basic pin functions are identical for each of the three channels (SCI3, SCI3_2, and SCI3_3), separate explanations are not given in this section.
17.1
Features
* Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected * External clock or on-chip baud rate generator can be selected as a transfer clock source. * Six interrupt sources Transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity error. * Noise canceller (only for SCI3_3) Asynchronous mode * * * * * Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RxD pin level directly in the case of a framing error
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Section 17 Serial Communication Interface 3 (SCI3)
Clocked synchronous mode * Data length: 8 bits * Receive error detection: Overrun errors Table 17.1 Channel Configuration
Channel Channel 1 Abbreviation SCI3*2 Pin SCK3 RXD TXD Register SMR BRR SCR3 TDR SSR RDR RSR TSR Channel 2 SCI3_2 SCK3_2 RXD_2 TXD_2 SMR_2 BRR_2 SCR3_2 TDR_2 SSR_2 RDR_2 RSR_2 TSR_2 Channel 3 SCI3_3 SCK3_3 RXD_3 TXD_3 SMR_3 BRR_3 SCR3_3 TDR_3 SSR_3 RDR_3 RSR_3 TSR_3 SMCR_3*
1
Register Address H'FFFFA8 H'FFFFA9 H'FFFFAA H'FFFFAB H'FFFFAC H'FFFFAD H'FFF740 H'FFF741 H'FFF742 H'FFF743 H'FFF744 H'FFF745 H'FFF600 H'FFF601 H'FFF602 H'FFF603 H'FFF604 H'FFF605 H'FFF608
Noise Canceller None
None
Yes
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Section 17 Serial Communication Interface 3 (SCI3)
Note:
1. In addition to basic functions common to SCI3 and SCI3_2, SCI3_3 has the serial mode control register (SMCR). SMCR controls taking noise from the RXD_3 input signal, P92/TxD_3 pin function, and SCI3_3 module standby function. 2. The channel 1 of the SCI3 is used in on-board programming mode by boot mode.
* Serial mode control register (SMCR)
Bit 7 to 3 2 Bit Name NFEN_3 Initial Value All 1 0 R/W R/W Description Reserved These bits are always read as 1. Noise Cancel Function Select When COM in SMR is cleared to 0 and this bit is set to 1, noise in the RXD_3 input signal is taken. 1 TXD_3 0 R/W TXD_3 Pin Select Selects P92/TXD_3 pin function. 0: General input pin is selected 1: TXD_3 output pin is selected 0 MSTS3_3 0 R/W SCI3_3 Module Standby When this bit is set to 1, SCI3_3 enters in the standby state.
* Noise canceller The RXD_3 input signal is loaded internally via the noise canceller. The noise canceller consists of three latch circuits and match detection circuit connected in series. The RXD_3 input signal is sampled on the basic clock with a frequency 16 times the transfer rate, and the level is passed forward to the next circuit when outputs of three latches match. When the outputs are not match, previous value is retained. In other word, when the same level is retained more than three clocks, the input signal is acknowledged as a signal. When the level is changed within three clocks, the change is acknowledged as not a signal change but noise.
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Section 17 Serial Communication Interface 3 (SCI3)
Sampling clock
RXD_3 input signal
D
C Q Latch
D
C Q Latch
D
C Q Latch
Match detector
SCMR3 (NFEF_3)
Internal RXD_3 signal in figure 17.1
Internal basic clock interval Sampling clock
Block Diagram of Noise Canceller
SCK3
External clock
Internal clock (/64, /16, /4, ) Baud rate generator
BRC Clock
BRR
Transmit/receive control circuit
SCR3 SSR
TXD TSR TDR
RXD
RSR
RDR Interrupt request (TEI, TXI, RXI, ERI)
[Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR3: Serial control register 3 SSR: Serial status register BRR: Bit rate register BRC: Bit rate counter
Figure 17.1 Block Diagram of SCI3
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Internal data bus
SMR
Section 17 Serial Communication Interface 3 (SCI3)
17.2
Input/Output Pins
Table 17.2 shows the SCI3 pin configuration. Table 17.2 Pin Configuration
Pin Name SCI3 clock SCI3 receive data input SCI3 transmit data output Abbreviation SCK3 RXD TXD I/O I/O Input Output Function SCI3 clock input/output SCI3 receive data input SCI3 transmit data output
17.3
Register Descriptions
The SCI3 has the following registers for each channel. * * * * * * * * * Receive Shift Register (RSR) Receive Data Register (RDR) Transmit Shift Register (TSR) Transmit Data Register (TDR) Serial Mode Register (SMR) Serial Control Register 3 (SCR3) Serial Status Register (SSR) Bit Rate Register (BRR) Serial mode control register 3 (SMCR3) Receive Shift Register (RSR)
17.3.1
RSR is a shift register that is used to receive serial data input from the RxD pin and convert it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 17.3.2 Receive Data Register (RDR)
RDR is an 8-bit register that stores received data. When the SCI3 has received one frame of serial data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR cannot be written to by the CPU. RDR is initialized to H'00.
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Section 17 Serial Communication Interface 3 (SCI3)
17.3.3
Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI3 first transfers transmit data from TDR to TSR automatically, then sends the data that starts from the LSB to the TXD pin. TSR cannot be directly accessed by the CPU. 17.3.4 Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The doublebuffered structure of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR during transmission of one-frame data, the SCI3 transfers the written data to TSR to continue transmission. To achieve reliable serial transmission, write transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is initialized to H'FF. 17.3.5 Serial Mode Register (SMR)
SMR is used to set the SCI3's serial transfer format and select the baud rate generator clock source.
Bit 7 Bit Name COM Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. 4 PM 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity.
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Section 17 Serial Communication Interface 3 (SCI3)
Bit 3
Bit Name STOP
Initial Value 0
R/W R/W
Description Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits For reception, only the first stop bit is checked, regardless of the value in the bit. If the second stop bit is 0, it is treated as the start bit of the next transmit character.
2
MP
0
R/W
Multiprocessor Mode When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and PM bit settings are invalid in multiprocessor mode. In clocked synchronous mode, clear this bit to 0.
1 0
CKS1 CKS0
0 0
R/W R/W
Clock Select 0 and 1 These bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 17.3.8, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 17.3.8, Bit Rate Register (BRR)).
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Section 17 Serial Communication Interface 3 (SCI3)
17.3.6
Serial Control Register 3 (SCR3)
SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is also used to select the transfer clock source. For details on interrupt requests, see section 17.7, Interrupt Requests.
Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, the TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 3 TE RE MPIE 0 0 0 R/W R/W R/W Transmit Enable When this bit s set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and OER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, see section 17.6, Multiprocessor Communication Function. 2 TEIE 0 R/W Transmit End Interrupt Enable When this bit is set to 1, TEI interrupt request is enabled.
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Section 17 Serial Communication Interface 3 (SCI3)
Bit 1 0
Bit Name CKE1 CKE0
Initial Value 0 0
R/W R/W R/W
Description Clock Enable 0 and 1 Selects the clock source. * Asynchronous mode 00: On-chip baud rate generator 01: On-chip baud rate generator Outputs a clock of the same frequency as the bit rate from the SCK3 pin. 10: External clock Inputs a clock with a frequency 16 times the bit rate from the SCK3 pin. 11:Reserved * Clocked synchronous mode 00: On-chip clock (SCK3 pin functions as clock output) 01:Reserved 10: External clock (SCK3 pin functions as clock input) 11:Reserved
17.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared.
Bit 7 Bit Name TDRE Initial Value 1 R/W R/W Description Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] * * * * When the TE bit in SCR3 is 0 When data is transferred from TDR to TSR When 0 is written to TDRE after reading TDRE = 1 When the transmit data is written to TDR
[Clearing conditions]
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Section 17 Serial Communication Interface 3 (SCI3)
Bit 6
Bit Name RDRF
Initial Value 0
R/W R/W
Description Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 When data is read from RDR
[Clearing conditions] * * 5 OER 0 R/W
Overrun Error [Setting condition] * * When an overrun error occurs in reception When 0 is written to OER after reading OER = 1 [Clearing condition]
4
FER
0
R/W
Framing Error [Setting condition] * * When a framing error occurs in reception When 0 is written to FER after reading FER = 1 [Clearing condition]
3
PER
0
R/W
Parity Error [Setting condition] * * When a parity error is detected during reception When 0 is written to PER after reading PER = 1 [Clearing condition]
2
TEND
1
R
Transmit End [Setting conditions] * * When the TE bit in SCR3 is 0 When TDRE = 1 at transmission of the last bit of a 1-frame serial transmit character When 0 is written to TDRE after reading TDRE = 1 When the transmit data is written to TDR
[Clearing conditions] * *
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Section 17 Serial Communication Interface 3 (SCI3)
Bit 1
Bit Name MPBR
Initial Value 0
R/W R
Description Multiprocessor Bit Receive MPBR stores the multiprocessor bit in the receive character data. When the RE bit in SCR3 is cleared to 0, its state is retained.
0
MPBT
0
R/W
Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to the transmit character data.
17.3.8
Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 17.3 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in asynchronous mode. Table 17.4 shows the maximum bit rate for each frequency in asynchronous mode. The values shown in both tables 17.3 and 17.4 are values in active (highspeed) mode. Table 17.5 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in clocked synchronous mode. The values shown in table 17.5 are values in active (high-speed) mode. The N setting in BRR and error for other operating frequencies and bit rates can be obtained by the following formulas: [Asynchronous Mode]
N= x 106 - 1 64 x 22n-1 x B
Error (%) =
x 106 - 1 x 100 (N + 1) x B x 64 x 22n-1
[Clocked Synchronous Mode]
N= x 106 - 1 8 x 22n-1 x B
[Legend] B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 N 255) : Operating frequency (MHz) n: CSK1 and CSK0 settings in SMR (0 n 3)
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Section 17 Serial Communication Interface 3 (SCI3)
Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
Operating Frequency (MHz) 2 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 0 0 0 0 N 141 103 207 103 51 25 12 6 2 1 1 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -6.99 8.51 0.00 -18.62 n 1 1 0 0 0 0 0 0 0 0 0 2.097152 N 148 108 217 108 54 26 13 6 2 1 1 Error (%) -0.04 0.21 0.21 0.21 -0.70 1.14 -2.48 -2.48 13.78 4.86 -14.67 n 1 1 0 0 0 0 0 0 0 0 0 2.4576 N 174 127 255 127 63 31 15 7 3 1 1 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 22.88 0.00 n 1 1 1 0 0 0 0 0 0 0 -- N 212 155 77 155 77 38 19 9 4 2 -- 3 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 --
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Section 17 Serial Communication Interface 3 (SCI3)
Operating Frequency (MHz) 3.6864 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 -- 0 N 64 191 95 191 95 47 23 11 5 -- 2 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 1 1 0 0 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 6 3 2 4 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -6.99 0.00 8.51 n 2 1 1 0 0 0 0 0 0 0 0 4.9152 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73
[Legend] : A setting is available but error occurs
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Section 17 Serial Communication Interface 3 (SCI3)
Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
Operating Frequency (MHz) 6 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 n 2 2 1 1 0 0 0 0 0 0 0 6.144 N 108 79 159 79 159 79 39 19 9 5 4 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 0 0 7.3728 N 130 95 191 95 191 95 47 23 11 6 5 Error (%) -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00
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Operating Frequency (MHz) 8 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 6 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -6.99 n 2 2 1 1 0 0 0 0 0 0 0 9.8304 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.00 -2.34
[Legend] : A setting is available but error occurs.
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Section 17 Serial Communication Interface 3 (SCI3)
Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3)
Operating Frequency (MHz) 12.888 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 0 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 2 1 1 0 0 0 0 0 -- N 248 181 90 181 90 181 90 45 22 13 -- 14 Error (%) -0.17 0.16 0.16 0.16 0.16 0.16 0.16 -0.93 -0.93 0.00 -- n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16
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Section 17 Serial Communication Interface 3 (SCI3)
Operating Frequency (MHz) 18 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 28 17 14 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.96 1.02 0.00 -2.34 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73
[Legend] --: A setting is available but error occurs.
Table 17.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
(MHz) 2 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 Maximum Bit Rate (bit/s) 62500 76800 93750 115200 125000 153600 156250 187500 192000 230400 n 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 (MHz) 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 20 Maximum Bit Rate (bit/s) 250000 307200 312500 375000 384000 437500 460800 500000 537600 562500 625000 n 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0
2.097152 65536
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Section 17 Serial Communication Interface 3 (SCI3)
Table 17.5 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1)
Operating Frequency (MHz) Bit Rate (bit/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2 n 3 2 1 1 0 0 0 0 0 0 0 0 N 70 124 249 124 199 99 49 19 9 4 1 0* n -- 2 2 1 1 0 0 0 0 0 0 0 0 4 N -- 249 124 249 99 199 99 39 19 9 3 1 0* n -- 3 2 2 1 1 0 0 0 0 0 0 0 0 8 N -- 124 249 124 199 99 199 79 39 19 7 3 1 0* n -- -- -- -- 1 1 0 0 0 0 0 0 -- -- 0 10 N -- -- -- -- 249 124 249 99 49 24 9 4 -- -- 0* n 3 3 2 2 1 1 0 0 0 0 0 0 0 -- 0 16 N 249 124 249 99 199 99 159 79 39 15 7 3 1 -- 0*
2M 2.5M 4M [Legend] Blank: No setting is available. --: A setting is available but error occurs. *: Continuous transfer is not possible.
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Section 17 Serial Communication Interface 3 (SCI3)
Table 17.5 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2)
Operating Frequency (MHz) Bit Rate (bit/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2M 2.5M 4M 18 n -- -- 3 3 2 1 1 0 0 0 0 0 0 -- -- -- N -- -- 140 69 112 224 112 179 89 44 17 8 4 -- -- -- n -- -- 3 3 2 1 1 0 0 0 0 0 0 -- 0 -- 20 N -- -- 155 77 124 249 124 199 99 49 19 9 4 -- 1 --
[Legend] Blank: No setting is available. --: A setting is available but error occurs. *: Continuous transfer is not possible.
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Section 17 Serial Communication Interface 3 (SCI3)
17.4
Operation in Asynchronous Mode
Figure 17.2 shows the general format for asynchronous serial communication. One character (or frame) consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex. Both the transmitter and the receiver also have a doublebuffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer.
LSB
Serial Start data bit Transmit/receive data
MSB
Parity bit
1
Stop bit
Mark state
1 bit
7 or 8 bits
One unit of transfer data (character or frame)
1 bit, or none
1 or 2 bits
Figure 17.2 Data Format in Asynchronous Communication 17.4.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK3 pin can be selected as the SCI3's serial clock, according to the setting of the COM bit in SMR and the CKE0 and CKE1 bits in SCR3. When an external clock is input at the SCK3 pin, the clock frequency should be 16 times the bit rate used. When the SCI3 is operated on an internal clock, the clock can be output from the SCK3 pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 17.3.
Clock Serial data
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 character (frame)
Figure 17.3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)
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Section 17 Serial Communication Interface 3 (SCI3)
17.4.2
SCI3 Initialization
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR3 to 0, then initialize the SCI3 as described below. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization.
[1] Start initialization Set the clock selection in SCR3. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock output is selected in asynchronous mode, clock is output immediately after CKE1 and CKE0 settings are made. When the clock output is selected at reception in clocked synchronous mode, clock is output immediately after CKE1, CKE0, and RE are set to 1. [2] Set value in BRR Wait No 1-bit interval elapsed? Yes Set TE and RE bits in SCR3 to 1, and set RIE, TIE, TEIE, and MPIE bits. For transmit (TE=1), also set the TxD bit in PMR1. [4] [3] [3] Set the data transfer format in SMR. Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. Wait at least one bit interval, then set the TE bit or RE bit in SCR3 to 1. RE settings enable the RXD pin to be used. For transmission, set the TXD bit in PMR1 to 1 to enable the TXD output pin to be used. Also set the RIE, TIE, TEIE, and MPIE bits, depending on whether interrupts are required. In asynchronous mode, the bits are marked at transmission and idled at reception to wait for the start bit.
Clear TE and RE bits in SCR3 to 0
Set CKE1 and CKE0 bits in SCR3
[1]
Set data transfer format in SMR
[2]
[4]

Figure 17.4 Sample SCI3 Initialization Flowchart
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Section 17 Serial Communication Interface 3 (SCI3)
17.4.3
Data Transmission
Figure 17.5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a TXI interrupt request is generated. Continuous transmission is possible because the TXI interrupt routine writes next transmit data to TDR before transmission of the current transmit data has been completed. 3. The SCI3 checks the TDRE flag at the timing for sending the stop bit. 4. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 5. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered, in which 1 is output. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt request is generated. 6. Figure 17.6 shows a sample flowchart for transmission in asynchronous mode.
Start bit Serial data 1 0 D0 D1 1 frame Transmit data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Transmit data D1 1 frame D7 Parity Stop bit bit 0/1 1 1 Mark state
TDRE TEND TXI interrupt LSI operation request generated User processing TDRE flag cleared to 0 Data written to TDR TXI interrupt request generated TEI interrupt request generated
Figure 17.5 Example of SCI3 Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)
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Section 17 Serial Communication Interface 3 (SCI3)
Start transmission
[1]
[1]
Read TDRE flag in SSR [2] TDRE = 1 Yes [3] Write transmit data to TDR No
Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. To output a break in serial transmission, after setting PCR to 1 and PDR to 0, clear TxD in PMR1 to 0, then clear the TE bit in SCR3 to 0.
[2]
All data transmitted? No
Yes
Read TEND flag in SSR
TEND = 1 Yes [3]
No
Break output? Yes Clear PDR to 0 and set PCR to 1
No
Clear TE bit in SCR3 to 0

Figure 17.6 Sample Serial Transmission Data Flowchart (Asynchronous Mode)
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Section 17 Serial Communication Interface 3 (SCI3)
17.4.4
Serial Data Reception
Figure 17.7 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI3 operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated. 5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is generated. Continuous reception is possible because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has been completed.
Start bit Serial data 1 0 D0 D1 1 frame Receive data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Receive data D1 1 frame D7 Parity Stop bit bit 0/1 0 Mark state (idle state) 1
RDRF FER LSI operation User processing RXI request RDRF cleared to 0 RDR data read 0 stop bit detected ERI request in response to framing error Framing error processing
Figure 17.7 Example of SCI3 Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)
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Section 17 Serial Communication Interface 3 (SCI3)
Table 17.6 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 17.8 shows a sample flow chart for serial data reception. Table 17.6 SSR Status Flags and Receive Data Handling
SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * OER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error
The RDRF flag retains the state it had before data reception.
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Section 17 Serial Communication Interface 3 (SCI3)
Start reception
Read OER, PER, and FER flags in SSR
[1]
[1]
Read the OER, PER, and FER flags in SSR to identify the error. If a receive error occurs, performs the appropriate error processing. Read SSR and check that RDRF = 1, then read the receive data in RDR. The RDRF flag is cleared automatically. To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag and read RDR. The RDRF flag is cleared automatically. If a receive error occurs, read the OER, PER, and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the OER, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1. In the case of a framing error, a break can be detected by reading the value of the input port corresponding to the RxD pin.
OER+PER+FER = 1 No
Yes [4] Error processing
[2]
[3] (Continued on next page) [2] [4]
Read RDRF flag in SSR
No
RDRF = 1 Yes Read receive data in RDR
Yes
All data received? No Clear RE bit in SCR3 to 0
[3]
(A)

Figure 17.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (1)
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Section 17 Serial Communication Interface 3 (SCI3)
[4]
Error processing
No
OER = 1
Yes
Overrun error processing
No
FER = 1
Yes Yes
Break?
No
Framing error processing
No
PER = 1
Yes
Parity error processing
(A)
Clear OER, PER, and FER flags in SSR to 0

Figure 17.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (2)
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Section 17 Serial Communication Interface 3 (SCI3)
17.5
Operation in Clocked Synchronous Mode
Figure 17.9 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the synchronization clock to the next. In clocked synchronous mode, the SCI3 receives data in synchronous with the rising edge of the synchronization clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI3, the transmitter and receiver are independent units, enabling fullduplex communication through the use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer.
8-bit One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care *
Figure 17.9 Data Format in Clocked Synchronous Communication 17.5.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK3 pin can be selected, according to the setting of the COM bit in SMR and CKE0 and CKE1 bits in SCR3. When the SCI3 is operated on an internal clock, the synchronization clock is output from the SCK3 pin. Eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. 17.5.2 SCI3 Initialization
Before transmitting and receiving data, the SCI3 should be initialized as described in a sample flowchart in figure 17.4.
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Section 17 Serial Communication Interface 3 (SCI3)
17.5.3
Serial Data Transmission
Figure 17.10 shows an example of SCI3 operation for transmission in clocked synchronous mode. In serial transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR3 is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the TxD pin. 4. The SCI3 checks the TDRE flag at the timing for sending the MSB (bit 7). 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the output state of the last bit. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt request is generated. 7. The SCK3 pin is fixed high at the end of transmission. Figure 17.11 shows a sample flow chart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1. Make sure that the receive error flags are cleared to 0 before starting transmission.
Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
1 frame TDRE TEND TXI interrupt LSI operation request generated User processing TDRE flag cleared to 0 Data written to TDR
1 frame
TXI interrupt request generated
TEI interrupt request generated
Figure 17.10 Example of SCI3 Transmission in Clocked Synchronous Mode
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Section 17 Serial Communication Interface 3 (SCI3)
Start transmission
[1]
[1]
Read TDRE flag in SSR
Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0 and clocks are output to start the data transmission. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0.
No TDRE = 1 Yes Write transmit data to TDR
[2]
[2]
All data transmitted? No
Yes
Read TEND flag in SSR
No TEND = 1 Yes Clear TE bit in SCR3 to 0
Figure 17.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)
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Section 17 Serial Communication Interface 3 (SCI3)
17.5.4
Serial Data Reception (Clocked Synchronous Mode)
Figure 17.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In serial reception, the SCI3 operates as described below. 1. 2. 3. The SCI3 performs internal initialization synchronous with a synchronization clock input or output, starts receiving data. The SCI3 stores the receive data in RSR. If an overrun error occurs (when reception of the next data is completed while the RDRF flag in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the RDRF flag remains to be set to 1. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is generated.
4.
Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
1 frame RDRF OER LSI operation User processing RXI interrupt request generated RDRF flag cleared to 0 RDR data read
1 frame
RXI interrupt request generated
ERI interrupt request generated by overrun error Overrun error processing
RDR data has not been read (RDRF = 1)
Figure 17.12 Example of SCI3 Reception in Clocked Synchronous Mode
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Section 17 Serial Communication Interface 3 (SCI3)
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 17.13 shows a sample flow chart for serial data reception.
Start reception [1] Read the OER flag in SSR to determine if there is an error. If an overrun error has occurred, execute overrun error processing. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF flag is automatically cleared to 0. To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag and reading RDR should be finished. When data is read from RDR, the RDRF flag is automatically cleared to 0. If an overrun error occurs, read the OER flag in SSR, and after performing the appropriate error processing, clear the OER flag to 0. Reception cannot be resumed if the OER flag is set to 1.
Read OER flag in SSR [1] Yes OER = 1 [4] No Error processing (Continued below) Read RDRF flag in SSR [2] [4] RDRF = 1 Yes Read receive data in RDR [3] [2]
No
Yes All data received? No Clear RE bit in SCR3 to 0 [3]
[4] Error processing
Overrun error processing
Clear OER flag in SSR to 0
Figure 17.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)
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Section 17 Serial Communication Interface 3 (SCI3)
17.5.5
Simultaneous Serial Data Transmission and Reception
Figure 17.14 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished reception, clear RE to 0. Then after checking that the RDRF and receive error flags (OER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction.
Start transmission/reception [1]
[1]
Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR Read OER flag in SSR
Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF flag is automatically cleared to 0. To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. When data is read from RDR, the RDRF flag is automatically cleared to 0. If an overrun error occurs, read the OER flag in SSR, and after performing the appropriate error processing, clear the OER flag to 0. Transmission/reception cannot be resumed if the OER flag is set to 1. For overrun error processing, see figure 17.13.
[2]
[3]
Yes OER = 1 No Read RDRF flag in SSR No RDRF = 1 [4] Yes Read receive data in RDR Yes All data received? No Clear TE and RE bits in SCR to 0 [4] Error processing [2]
[3]
Figure 17.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations (Clocked Synchronous Mode)
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Section 17 Serial Communication Interface 3 (SCI3)
17.6
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles; an ID transmission cycle that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 17.15 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI3 uses the MPIE bit in SCR3 to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and OER, to 1, are inhibited until data with a 1 multiprocessor bit is received. On reception of a receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode.
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Section 17 Serial Communication Interface 3 (SCI3)
Transmitting station Serial transmission line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) H'01 (MPB = 1) Receiving station C (ID = 03) H'AA (MPB = 0) Receiving station D (ID = 04)
[Legend] MPB: Multiprocessor bit
ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID
Figure 17.15 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
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Section 17 Serial Communication Interface 3 (SCI3)
17.6.1
Multiprocessor Serial Data Transmission
Figure 17.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same as those in asynchronous mode.
Start transmission
[1]
[1]
Read TDRE flag in SSR No TDRE = 1 [2] Yes Set MPBT bit in SSR Write transmit data to TDR [3] Yes
Read SSR and check that the TDRE flag is set to 1, set the MPBT bit in SSR to 0 or 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. To output a break in serial transmission, set the port PCR to 1, clear PDR to 0, then clear the TE bit in SCR3 to 0.
[2]
All data transmitted? No Read TEND flag in SSR No TEND = 1 Yes No
[3]
Break output? Yes Clear PDR to 0 and set PCR to 1 Clear TE bit in SCR3 to 0

Figure 17.16 Sample Multiprocessor Serial Transmission Flowchart
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Section 17 Serial Communication Interface 3 (SCI3)
17.6.2
Multiprocessor Serial Data Reception
Figure 17.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI3 operations are the same as those in asynchronous mode. Figure 17.18 shows an example of SCI3 operation for multiprocessor format reception.
Start reception Set MPIE bit in SCR3 to 1 Read OER and FER flags in SSR FER+OER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR No [3] [1] [2] Yes
[1] [2]
Set the MPIE bit in SCR3 to 1. Read OER and FER in SSR to check for errors. Receive error processing is performed in cases where a receive error occurs. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again. When data is read from RDR, the RDRF flag is automatically cleared to 0. Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. If a receive error occurs, read the OER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the OER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value.
[3]
[4]
[5] This station's ID? Yes Read OER and FER flags in SSR Yes FER+OER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR [4] [5] Error processing
(Continued on next page)
Yes
All data received? No [A] Clear RE bit in SCR3 to 0
Figure 17.17 Sample Multiprocessor Serial Reception Flowchart (1)
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Section 17 Serial Communication Interface 3 (SCI3)
[5]
Error processing
No OER = 1 Yes Overrun error processing
No FER = 1 Yes Yes Break? No Framing error processing [A]
Clear OER, and FER flags in SSR to 0

Figure 17.17 Sample Multiprocessor Serial Reception Flowchart (2)
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Section 17 Serial Communication Interface 3 (SCI3)
Start bit Serial data 1 0 D0
Receive data (ID1) D1 1 frame D7
MPB 1
Stop Start bit bit 1 0 D0
Receive data (Data1) D1 1 frame D7
MPB 0
Stop bit 1
Mark state (idle state) 1
MPIE
RDRF RDR value LSI operation User processing RXI interrupt request MPIE cleared to 0 RDRF flag cleared to 0 RDR data read When data is not this station's ID, MPIE is set to 1 again ID1
RXI interrupt request is not generated, and RDR retains its state
(a) When data does not match this receiver's ID
Start bit Serial data 1 0 D0
Receive data (ID2) D1 1 frame D7
MPB 1
Stop Start bit bit 1 0 D0
Receive data (Data2) D1 1 frame D7
MPB 0
Stop bit 1
Mark state (idle state) 1
MPIE
RDRF RDR value LSI operation User processing ID1 ID2 Data2
RXI interrupt request MPIE cleared to 0
RDRF flag cleared to 0 RDR data read
RXI interrupt request When data is this station's ID, reception is continued
RDRF flag cleared to 0 RDR data read MPIE set to 1 again
(b) When data matches this receiver's ID
Figure 17.18 Example of SCI3 Reception Using Multiprocessor Format (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
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Section 17 Serial Communication Interface 3 (SCI3)
17.7
Interrupt Requests
SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 17.7 shows the interrupt sources. Table 17.7 SCI3 Interrupt Requests
Interrupt Requests Receive Data Full Transmit Data Empty Transmission End Receive Error Abbreviation RXI TXI TEI ERI Interrupt Sources Setting RDRF in SSR Setting TDRE in SSR Setting TEND in SSR Setting OER, FER, and PER in SSR
The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR3 is set to 1 before transferring the transmit data to TDR, a TXI interrupt request is generated even if the transmit data is not ready. The initial value of the TEND flag in SSR is 1. Thus, when the TEIE bit in SCR3 is set to 1 before transferring the transmit data to TDR, a TEI interrupt request is generated even if the transmit data has not been sent. It is possible to make use of the most of these interrupt requests efficiently by transferring the transmit data to TDR in the interrupt routine. To prevent the generation of these interrupt requests (TXI and TEI), set the enable bits (TIE and TEIE) that correspond to these interrupt requests to 1, after transferring the transmit data to TDR.
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Section 17 Serial Communication Interface 3 (SCI3)
17.8
17.8.1
Usage Notes
Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, setting the FER flag, and possibly the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 17.8.2 Mark State and Break Sending
When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by PCR and PDR. This can be used to set the TxD pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both PCR and PDR to 1. As TE is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set PCR to 1 and clear PDR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 17.8.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.
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Section 17 Serial Communication Interface 3 (SCI3)
17.8.4
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 17.19. Thus, the reception margin in asynchronous mode is given by formula (1) below.
1 D - 0.5 M = (0.5 - )- - (L - 0.5) F x 100(%) 2N N
... Formula (1)
[Legend] N: Ratio of bit rate to clock (N = 16) D: Clock duty (D = 0.5 to 1.0) L: Frame length (L = 9 to 12) F: Absolute value of clock rate deviation
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula.
M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design.
16 clocks 8 clocks 0 Internal basic clock Receive data (RxD) Synchronization sampling timing Data sampling timing 7 15 0 7 15 0
Start bit
D0
D1
Figure 17.19 Receive Data Sampling Timing in Asynchronous Mode
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Section 18 I C Bus Interface 2 (IIC2)
2
Section 18 I2C Bus Interface 2 (IIC2)
The I2C bus interface 2 conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. Figure 18.1 shows a block diagram of the I2C bus interface 2. Figure 18.2 shows an example of I/O pin connections to external circuits.
18.1
Features
* Selection of I2C format or clocked synchronous serial format * Continuous transmission/reception Since the shift register, transmit data register, and receive data register are independent from each other, the continuous transmission/reception can be performed. I2C bus format * Start and stop conditions generated automatically in master mode * Selection of acknowledge output levels when receiving * Automatic loading of acknowledge bit when transmitting * Bit synchronization/wait function In master mode, the state of SCL is monitored per bit, and the timing is synchronized automatically. If transmission/reception is not yet possible, set the SCL to low until preparations are completed. * Six interrupt sources Transmit data empty (including slave-address match), transmit end, receive data full (including slave-address match), arbitration lost, NACK detection, and stop condition detection * Direct bus drive Two pins, SCL and SDA pins, function as NMOS open-drain outputs when the bus drive function is selected. Clocked synchronous format * Four interrupt sources Transmit-data-empty, transmit-end, receive-data-full, and overrun error
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Section 18 I C Bus Interface 2 (IIC2)
2
Transfer clock generation circuit
SCL
Output control
Transmission/ reception control circuit
ICCR1 ICCR2 ICMR
Noise canceler ICDRT SAR
SDA
Output control
ICDRS
Noise canceler
Address comparator ICDRR Bus state decision circuit Arbitration decision circuit ICIER
ICSR
[Legend] ICCR1: I2C bus control register 1 ICCR2: I2C bus control register 2 ICMR: I2C bus mode register ICSR: I2C bus status register ICIER: I2C bus interrupt enable register ICDRT: I2C bus transmit data register ICDRR: I2C bus receive data register ICDRS: I2C bus shift register SAR: Slave address register
Interrupt generator
Internal data bus
Interrupt request
Figure 18.1 Block Diagram of I2C Bus Interface 2
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Section 18 I C Bus Interface 2 (IIC2)
2
Vcc
Vcc
SCL in SCL out
SCL
SCL
SDA in SDA out (Master)
SDA
SDA
SCL SDA
SCL in SCL out SDA in SDA out (Slave 1)
SCL in SCL out SDA in SDA out (Slave 2)
Figure 18.2 External Circuit Connections of I/O Pins
18.2
Input/Output Pins
Table 18.1 summarizes the input/output pins used by the I2C bus interface 2. Table 18.1 Pin Configuration
Name Serial clock Serial data Abbreviation SCL SDA I/O I/O I/O Function IIC serial clock input/output IIC serial data input/output
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SCL SDA
Section 18 I C Bus Interface 2 (IIC2)
2
18.3
Register Descriptions
The I2C bus interface 2 has the following registers. * * * * * * * * * I2C bus control register 1 (ICCR1) I2C bus control register 2 (ICCR2) I2C bus mode register (ICMR) I2C bus interrupt enable register (ICIER) I2C bus status register (ICSR) I2C bus slave address register (SAR) I2C bus transmit data register (ICDRT) I2C bus receive data register (ICDRR) I2C bus shift register (ICDRS) I2C Bus Control Register 1 (ICCR1)
18.3.1
ICCR1 enables or disables the I2C bus interface 2, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode.
Bit 7 Bit Name ICE Initial Value 0 R/W R/W Description I2C Bus Interface Enable 0: This module is halted. (SCL and SDA pins are set to port function.) 1: This bit is enabled for transfer operations. (SCL and SDA pins are bus drive state.) Reception Disable This bit enables or disables the next operation when TRS is 0 and ICDRR is read. 0: Enables next reception 1: Disables next reception
6
RCVD
0
R/W
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Section 18 I C Bus Interface 2 (IIC2)
2
Bit 5 4
Bit Name MST TRS
Initial Value 0 0
R/W R/W R/W
Description Master/Slave Select Transmit/Receive Select 2 In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames. After data receive has been started in slave receive mode, when the first seven bits of the receive data agree with the slave address that is set to SAR and the eighth bit is 1, TRS is automatically set to 1. If an overrun error occurs in master mode with the clock synchronous serial format, MST is cleared to 0 and slave receive mode is entered. Operating modes are described below according to MST and TRS combination. When clocked synchronous serial format is selected and MST is 1, clock is output. 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode Transfer Clock Select 3 to 0 These bits should be set according to the necessary transfer rate (see table 18.2) in master mode. In slave mode, these bits are used for reservation of the setup time in transmit mode. The time is 10 tcyc when CKS3 = 0 and 20 tcyc when CKS3 = 1.
3 2 1 0
CKS3 CKS2 CKS1 CKS0
0 0 0 0
R/W R/W R/W R/W
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Section 18 I C Bus Interface 2 (IIC2)
2
Table 18.2 Transfer Rate
Bit 3 CKS3 0 Bit 2 CKS2 0 Bit 1 CKS1 0 1 1 0 1 1 0 0 1 1 0 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock =5 MHz /28 /40 /48 /64 /80 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz =8 MHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz 143 kHz 100 kHz 83.3 kHz 62.5 kHz 50.0 kHz 40.0 kHz 35.7 kHz 31.3 kHz Transfer Rate =10 MHz =16 MHz =20 MHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz 571 kHz 400 kHz 333 kHz 250 kHz 200 kHz 160 kHz 143 kHz 125 kHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz 714 kHz 500 kHz 417 kHz 313 kHz 250 kHz 200 kHz 179 kHz 156 kHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz
/100 50.0 kHz /112 44.6 kHz /128 39.1 kHz /56 /80 /96 89.3 kHz 62.5 kHz 52.1 kHz
/128 39.1 kHz /160 31.3 kHz /200 25.0 kHz /224 22.3 kHz /256 19.5 kHz
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Section 18 I C Bus Interface 2 (IIC2)
2
18.3.2
I2C Bus Control Register 2 (ICCR2)
ICCR2 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in the control part of the I2C bus interface 2.
Bit 7 Bit Name BBSY Initial Value 0 R/W R/W Description Bus Busy This bit enables to confirm whether the I C bus is occupied or released and to issue start/stop conditions in master mode. With the clocked synchronous serial 2 format, this bit has no meaning. With the I C bus format, this bit is set to 1 when the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. This bit is cleared to 0 when the SDA level changes from low to high under the condition of SCL = high, assuming that the stop condition has been issued. Write 1 to BBSY and 0 to SCP to issue a start condition. Follow this procedure when also re-transmitting a start condition. Write 0 in BBSY and 0 in SCP to issue a stop condition. To issue start/stop conditions, use the MOV instruction. 6 SCP 1 W Start/Stop Issue Condition Disable The SCP bit controls the issue of start/stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. If 1 is written, the data is not stored. 5 SDAO 1 R/W SDA Output Value Control This bit is used with SDAOP when modifying output level of SDA. This bit should not be manipulated during transfer. 0: When reading, SDA pin outputs low. When writing, SDA pin is changed to output low. 1: When reading, SDA pin outputs high. When writing, SDA pin is changed to output Hi-Z (outputs high by external pull-up resistance).
2
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Section 18 I C Bus Interface 2 (IIC2)
2
Bit 4
Bit Name SDAOP
Initial Value 1
R/W R/W
Description SDAO Write Protect This bit controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0 by the MOV instruction. This bit is always read as 1.
3
SCLO
1
R
This bit monitors SCL output level. When SCLO is 1, SCL pin outputs high. When SCLO is 0, SCL pin outputs low. Reserved This bit is always read as 1. IIC Control Part Reset This bit resets the control part except for I C registers. If this bit is set to 1 when hang-up occurs because of 2 2 communication failure during I C operation, I C control part can be reset without setting ports and initializing registers.
2
2 1
IICRST
1 0
R/W
0
1
Reserved This bit is always read as 1.
18.3.3
I2C Bus Mode Register (ICMR)
ICMR selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the transfer bit count.
Bit 7 Bit Name MLS Initial Value 0 R/W R/W Description MSB-First/LSB-First Select 0: MSB-first 1: LSB-first Set this bit to 0 when the I2C bus format is used.
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Section 18 I C Bus Interface 2 (IIC2)
2
Bit 6
Bit Name WAIT
Initial Value 0
R/W R/W
Description Wait Insertion Bit In master mode with the I2C bus format, this bit selects whether to insert a wait after data transfer except the acknowledge bit. When WAIT is set to 1, after the fall of the clock for the final data bit, low period is extended for two transfer clocks. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. The setting of this bit is invalid in slave mode with the I2C bus format or with the clocked synchronous serial format. Reserved These bits are always read as 1. BC Write Protect This bit controls the BC2 to BC0 modifications. When modifying BC2 to BC0, this bit should be cleared to 0 and use the MOV instruction. In clock synchronous serial mode, BC should not be modified. 0: When writing, values of BC2 to BC0 are set. 1: When reading, 1 is always read. When writing, settings of BC2 to BC0 are invalid. Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits 2 is indicated. With the I C bus format, the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL pin is low. The value returns to 000 at the end of a data transfer, including the acknowledge bit. With the clock synchronous serial format, these bits should not be modified. I2C Bus Format Clock Synchronous Serial Format 000: 9 bits 000: 8 bits 001: 2 bits 001: 1 bits 010: 3 bits 010: 2 bits 011: 4 bits 011: 3 bits 100: 5 bits 100: 4 bits 101: 6 bits 101: 5 bits 110: 7 bits 110: 6 bits 111: 8 bits 111: 7 bits
5 4 3
BCWP
1 1 1
R/W
2 1 0
BC2 BC1 BC0
0 0 0
R/W R/W R/W
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Section 18 I C Bus Interface 2 (IIC2)
2
18.3.4
I2C Bus Interrupt Enable Register (ICIER)
ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be received.
Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty interrupt (TXI). 0: Transmit data empty interrupt request (TXI) is disabled. 1: Transmit data empty interrupt request (TXI) is enabled. 6 TEIE 0 R/W Transmit End Interrupt Enable This bit enables or disables the transmit end interrupt (TEI) at the rising of the ninth clock while the TDRE bit in ICSR is 1. TEI can be canceled by clearing the TEND bit or the TEIE bit to 0. 0: Transmit end interrupt request (TEI) is disabled. 1: Transmit end interrupt request (TEI) is enabled. 5 RIE 0 R/W Receive Interrupt Enable This bit enables or disables the receive data full interrupt request (RXI) and the overrun error interrupt request (ERI) with the clocked synchronous format, when a receive data is transferred from ICDRS to ICDRR and the RDRF bit in ICSR is set to 1. RXI can be canceled by clearing the RDRF or RIE bit to 0. 0: Receive data full interrupt request (RXI) and overrun error interrupt request (ERI) with the clocked synchronous format are disabled. 1: Receive data full interrupt request (RXI) and overrun error interrupt request (ERI) with the clocked synchronous format are enabled.
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Section 18 I C Bus Interface 2 (IIC2)
2
Bit 4
Bit Name NAKIE
Initial Value 0
R/W R/W
Description NACK Receive Interrupt Enable This bit enables or disables the NACK receive interrupt request (NAKI) and the overrun error (setting of the OVE bit in ICSR) interrupt request (ERI) with the clocked synchronous format, when the NACKF and AL bits in ICSR are set to 1. NAKI can be canceled by clearing the NACKF, OVE, or NAKIE bit to 0. 0: NACK receive interrupt request (NAKI) is disabled. 1: NACK receive interrupt request (NAKI) is enabled.
3
STIE
0
R/W
Stop Condition Detection Interrupt Enable 0: Stop condition detection interrupt request (STPI) is disabled. 1: Stop condition detection interrupt request (STPI) is enabled.
2
ACKE
0
R/W
Acknowledge Bit Judgement Select 0: The value of the receive acknowledge bit is ignored, and continuous transfer is performed. 1: If the receive acknowledge bit is 1, continuous transfer is halted.
1
ACKBR
0
R
Receive Acknowledge In transmit mode, this bit stores the acknowledge data that are returned by the receive device. This bit cannot be modified. 0: Receive acknowledge = 0 1: Receive acknowledge = 1
0
ACKBT
0
R/W
Transmit Acknowledge In receive mode, this bit specifies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing. 1: 1 is sent at the acknowledge timing.
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Section 18 I C Bus Interface 2 (IIC2)
2
18.3.5
I2C Bus Status Register (ICSR)
ICSR performs confirmation of interrupt request flags and status.
Bit 7 Bit Name TDRE Initial Value 0 R/W R/W Description Transmit Data Register Empty [Setting conditions] * * * * When data is transferred from ICDRT to ICDRS and ICDRT becomes empty When TRS is set When a start condition (including re-transfer) has been issued When transmit mode is entered from receive mode in slave mode When 0 is written in TDRE after reading TDRE = 1 When data is written to ICDRT with an instruction
[Clearing conditions] * * 6 TEND 0 R/W
Transmit End [Setting conditions] * * When the ninth clock of SCL rises with the I C bus format while the TDRE flag is 1 When the final bit of transmit frame is sent with the clock synchronous serial format When 0 is written in TEND after reading TEND = 1 When data is written to ICDRT with an instruction
2
[Clearing conditions] * * 5 RDRF 0 R/W
Receive Data Register Full [Setting condition] * When a receive data is transferred from ICDRS to ICDRR When 0 is written in RDRF after reading RDRF = 1 When ICDRR is read with an instruction
[Clearing conditions] * *
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Section 18 I C Bus Interface 2 (IIC2)
2
Bit 4
Bit Name NACKF
Initial Value 0
R/W R/W
Description No Acknowledge Detection Flag [Setting condition] * When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 When 0 is written in NACKF after reading NACKF = 1
[Clearing condition] * 3 STOP 0 R/W
Stop Condition Detection Flag [Setting conditions] * * In master mode, when a stop condition is detected after frame transfer In slave mode, when a stop condition is detected after the general call address or the first byte slave address, next to detection of start condition, accords with the address set in SAR When 0 is written in STOP after reading STOP = 1
[Clearing condition] *
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Section 18 I C Bus Interface 2 (IIC2)
2
Bit 2
Bit Name AL/OVE
Initial Value 0
R/W R/W
Description Arbitration Lost Flag/Overrun Error Flag This flag indicates that arbitration was lost in master 2 mode with the I C bus format and that the final bit has been received while RDRF = 1 with the clocked synchronous format. When two or more master devices attempt to seize the 2 bus at nearly the same time, if the I C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been taken by another master. [Setting conditions] * * * If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode When the SDA pin outputs high in master mode while a start condition is detected When the final bit is received with the clocked synchronous format while RDRF = 1 When 0 is written in AL/OVE after reading AL/OVE=1
[Clearing condition] * 1 AAS 0 R/W
Slave Address Recognition Flag In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting conditions] * * When the slave address is detected in slave receive mode When the general call address is detected in slave receive mode. When 0 is written in AAS after reading AAS=1
[Clearing condition] *
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Section 18 I C Bus Interface 2 (IIC2)
2
Bit 0
Bit Name ADZ
Initial Value 0
R/W R/W
Description General Call Address Recognition Flag This bit is valid in I C bus format slave receive mode. [Setting condition] * When the general call address is detected in slave receive mode When 0 is written in ADZ after reading ADZ=1
2
[Clearing condition] *
18.3.6
Slave Address Register (SAR)
SAR selects the communication format and sets the slave address. When the chip is in slave mode with the I2C bus format, if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device.
Bit 7 to 1 Bit Name SVA6 to SVA0 Initial Value All 0 R/W R/W Description Slave Address 6 to 0 These bits set a unique address in bits SVA6 to SVA0, differing form the addresses of other slave devices 2 connected to the I C bus. 0 R/W Format Select 0: I C bus format is selected. 1: Clocked synchronous serial format is selected.
2
0
FS
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18.3.7
I2C Bus Transmit Data Register (ICDRT)
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible. If the MLS bit of ICMR is set to 1 and when the data is written to ICDRT, the MSB/LSB inverted data is read. The initial value of ICDRT is H'FF. 18.3.8 I2C Bus Receive Data Register (ICDRR)
ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a receive-only register, therefore the CPU cannot write to this register. The initial value of ICDRR is H'FF. 18.3.9 I2C Bus Shift Register (ICDRS)
ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the CPU.
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18.4
Operation
The I2C bus interface can communicate either in I2C bus mode or clocked synchronous serial mode by setting FS in SAR. 18.4.1 I2C Bus Format
Figure 18.3 shows the I2C bus formats. Figure 18.4 shows the I2C bus timing. The first frame following a start condition always consists of 8 bits.
(a) I2C bus format (FS = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 n: Transfer bit count (n = 1 to 8) m: Transfer frame count (m 1)
(b) I2C bus format (Start condition retransmission, FS = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 A/A 1 P 1
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8) m1 and m2: Transfer frame count (m1 and m2 1)
Figure 18.3 I2C Bus Formats
SDA
SCL S
1-7 SLA
8 R/W
9 A
1-7 DATA
8
9 A
1-7 DATA
8
9 A P
Figure 18.4 I2C Bus Timing
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[Legend] S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receive device drives SDA to low. DATA: Transfer data P: Stop condition. The master device drives SDA from low to high while SCL is high.
18.4.2
Master Transmit Operation
In master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For master transmit mode operation timing, see figures 18.5 and 18.6. The transmission procedure and operations in master transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. Read the BBSY flag in ICCR2 to confirm that the bus is free. Set the MST and TRS bits in ICCR1 to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using MOV instruction. (Start condition issued) This generates the start condition. 3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data show the slave address and R/W) to ICDRT. At this time, TDRE is automatically cleared to 0, and data is transferred from ICDRT to ICDRS. TDRE is set again. 4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1 at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the slave device has been selected. Then, write second byte data to ICDRT. When ACKBR is 1, the slave device has not been acknowledged, so issue the stop condition. To issue the stop condition, write 0 to BBSY and SCP using MOV instruction. SCL is fixed low until the transmit data is prepared or the stop condition is issued. 5. The transmit data after the second byte is written to ICDRT every time TDRE is set. 6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or NACKF. 7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
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SCL (Master output) SDA (Master output)
1 Bit 7
2 Bit 6
3 Bit 5
4 Bit 4
5 Bit 3
6 Bit 2
7 Bit 1
8 Bit 0 R/W
9
1 Bit 7
2 Bit 6
Slave address SDA (Slave output) TDRE
A
TEND
ICDRT
Address + R/W
Data 1
Data 2
ICDRS
Address + R/W
Data 1
User [2] Instruction of start processing condition issuance
[4] Write data to ICDRT (second byte) [3] Write data to ICDRT (first byte) [5] Write data to ICDRT (third byte)
Figure 18.5 Master Transmit Mode Operation Timing (1)
SCL (Master output) SDA (Master output) SDA (Slave output) TDRE A
9
1 Bit 7
2 Bit 6
3 Bit 5
4 Bit 4
5 Bit 3
6 Bit 2
7 Bit 1
8 Bit 0
9
A/A
TEND
ICDRT
Data n
ICDRS
Data n
User [5] Write data to ICDRT processing
[6] Issue stop condition. Clear TEND. [7] Set slave receive mode
Figure 18.6 Master Transmit Mode Operation Timing (2)
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18.4.3
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, see figures 18.7 and 18.8. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master transmit mode to master receive mode. Then, clear the TDRE bit to 0. 2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. The master device outputs the level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse. 3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF is cleared to 0. 4. The continuous reception is performed by reading ICDRR every time RDRF is set. If 8th receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is fixed low until ICDRR is read. 5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR. This enables the issuance of the stop condition after the next reception. 6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, issue the stage condition. 7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0. 8. The operation returns to the slave receive mode.
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Master transmit mode SCL (Master output) SDA (Master output) SDA (Slave output) TDRE A 9 1
Master receive mode 2 3 4 5 6 7 8 9 A 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
TEND
TRS
RDRF
ICDRS
Data 1
ICDRR User processing
Data 1 [3] Read ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read)
Figure 18.7 Master Receive Mode Operation Timing (1)
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SCL (Master output) SDA (Master output) SDA (Slave output) RDRF
9 A
1
2
3
4
5
6
7
8
9 A/A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RCVD
ICDRS
Data n-1
Data n
ICDRR User processing
Data n-1
Data n
[5] Read ICDRR after setting RCVD
[7] Read ICDRR, and clear RCVD
[6] Issue stop condition [8] Set slave receive mode
Figure 18.8 Master Receive Mode Operation Timing (2) 18.4.4 Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. For slave transmit mode operation timing, see figures 18.9 and 18.10. The transmission procedure and operations in slave transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS and ICSR bits in ICCR1 are set to 1, and the mode changes to slave transmit mode automatically. The continuous transmission is performed by writing transmit data to ICDRT every time TDRE is set. 3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1, with TDRE = 1. When TEND is set, clear TEND. 4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free. 5. Clear TDRE.
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Slave receive mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) TDRE TEND TRS ICDRT
Slave transmit mode 9 1 2 3 4 5 6 7 8 9 A 1
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Data 1
Data 2
Data 3
ICDRS
Data 1
Data 2
ICDRR User processing [2] Write data to ICDRT (data 1) [2] Write data to ICDRT (data 2) [2] Write data to ICDRT (data 3)
Figure 18.9 Slave Transmit Mode Operation Timing (1)
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Slave receive mode Slave transmit mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output)
TDRE TEND TRS ICDRT ICDRS ICDRR User processing 9 A 1 2 3 4 5 6 7 8 9
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data n
[3] Clear TEND
[4] Read ICDRR (dummy read) after clearing TRS
[5] Clear TDRE
Figure 18.10 Slave Transmit Mode Operation Timing (2) 18.4.5 Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For slave receive mode operation timing, see figures 18.11 and 18.12. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the read data show the slave address and R/W, it is not used.) 3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be returned to the master device, is reflected to the next transmit frame.
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Section 18 I C Bus Interface 2 (IIC2)
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4. The last byte data is read by reading ICDRR.
SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) RDRF A A
9
1
2
3
4
5
6
7
8
9
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
ICDRS
Data 1
Data 2
ICDRR User processing
Data 1
[2] Read ICDRR (dummy read)
[2] Read ICDRR
Figure 18.11 Slave Receive Mode Operation Timing (1)
SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output)
9
1
Bit 7
2
Bit 6
3
Bit 5
4
Bit 4
5
Bit 3
6
Bit 2
7
Bit 1
8
Bit 0
9
A
A
RDRF
ICDRS
Data 1
Data 2
ICDRR
User processing
Data 1
[3] Set ACKBT
[3] Read ICDRR [4] Read ICDRR
Figure 18.12 Slave Receive Mode Operation Timing (2)
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18.4.6
Clocked Synchronous Serial Format
This module can be operated with the clocked synchronous serial format, by setting the FS bit in SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When MST is 0, the external clock input is selected. Data Transfer Format Figure 18.13 shows the clocked synchronous serial transfer format. The transfer data is output from the rise to the fall of the SCL clock, and the data at the rising edge of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer, in either the MSB first or LSB first. The output level of SDA can be changed during the transfer wait, by the SDAO bit in ICCR2.
SCL
SDA
Bit 0
Bit 1
Bit 2 Bit 3 Bit 4
Bit 5 Bit 6
Bit 7
Figure 18.13 Clocked Synchronous Serial Transfer Format Transmit Operation In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For transmit mode operation timing, see figure 18.14. The transmission procedure and operations in transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. Set the TRS bit in ICCR1 to select the transmit mode. Then, TDRE in ICSR is set. 3. Confirm that TDRE has been set. Then, write the transmit data to ICDRT. The data is transferred from ICDRT to ICDRS, and TDRE is set automatically. The continuous transmission is performed by writing data to ICDRT every time TDRE is set. When changing from transmit mode to receive mode, clear TRS while TDRE is 1.
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SCL SDA (Output) TRS TDRE ICDRT ICDRS
1
2
7 Bit 6
8 Bit 7
1 Bit 0
7 Bit 6
8 Bit 7
1 Bit 0
Bit 0
Bit 1
Data 1 Data 1
Data 2 Data 2
Data 3 Data 3
User processing
[3] Write data [3] Write data to ICDRT to ICDRT [2] Set TRS
[3] Write data to ICDRT
[3] Write data to ICDRT
Figure 18.14 Transmit Mode Operation Timing Receive Operation In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, see figure 18.15. The reception procedure and operations in receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. When the transfer clock is output, set MST to 1 to start outputting the receive clock. 3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is continually output. The continuous reception is performed by reading ICDRR every time RDRF is set. When the 8th clock is risen while RDRF is 1, the overrun is detected and AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR. 4. To stop receiving when MST = 1, set RCVD in ICCR1 to 1, then read ICDRR. Then, SCL is fixed high after receiving the next byte data.
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2
SCL SDA (Input) MST TRS
1
2
7 Bit 6
8 Bit 7
1 Bit 0
7 Bit 6
8 Bit 7
1
2 Bit 0
Bit 0
Bit 1
RDRF ICDRS ICDRR User processing [2] Set MST (when outputting the clock) Data 1 Data 2 Data 3
Data 1
Data 2
[3] Read ICDRR
[3] Read ICDRR
Figure 18.15 Receive Mode Operation Timing 18.4.7 Noise Canceller
The logic levels at the SCL and SDA pins are routed through noise cancellers before being latched internally. Figure 18.16 shows a block diagram of the noise canceller circuit. The noise canceller consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
C SCL or SDA input signal D Latch Q D
C Q Latch March detector Internal SCL or SDA signal
System clock period Sampling clock
Figure 18.16 Block Diagram of Noise Canceller
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2
18.4.8
Example of Use
Flowcharts in respective modes that use the I2C bus interface are shown in figures 18.17 to 18.20.
Start Initialize Read BBSY in ICCR2 No BBSY=0 ? Yes Set MST and TRS in ICCR1 to 1. Write 1 to BBSY and 0 to SCP. Write transmit data in ICDRT Read TEND in ICSR No TEND=1 ? Yes Read ACKBR in ICIER ACKBR=0 ? No [1] [3] [2] [4] [3] [5] [4] [6] [7] [5] [8] [9] Issue the start candition. Set the first byte (slave address + R/W) of transmit data. Wait for 1 byte to be transmitted. Test the acknowledge transferred from the specified slave device. Set the second and subsequent bytes (except for the final byte) of transmit data. Wait for ICDRT empty. Set the last byte of transmit data. [1] [2] Test the status of the SCL and SDA lines. Set master transmit mode.
[6] [10] Wait for last byte to be transmitted. [11] Clear the TEND flag. Mater receive mode [7] [12] Clear the STOP flag. [13] Issue the stop condition. [8] [14] Wait for the creation of stop condition. [15] Set slave receive mode. Clear TDRE. [9]
Yes No Transmit mode? Yes Write transmit data in ICDRT Read TDRE in ICSR No TDRE=1 ? Yes No Last byte?
Yes Write transmit data in ICDRT Read TEND in ICSR No
[10] TEND=1 ? Yes Clear TEND in ICSR Clear STOP in ICSR Write 0 to BBSY and SCP Read STOP in ICSR [11] [12] [13]
No
[14] STOP=1 ? Yes Set MST to 1 and TRS to 0 in ICCR1 Clear TDRE in ICSR End
[15]
Figure 18.17 Sample Flowchart for Master Transmit Mode
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Mater receive mode [1] Clear TEND, select master receive mode, and then clear TDRE.* Clear TEND in ICSR Clear TRS in ICCR1 to 0 Clear TDRE in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR Read RDRF in ICSR No RDRF=1 ? Yes Last receive - 1? No Read ICDRR Yes [1] [2] Set acknowledge to the transmit device.* [3] Dummy-read ICDDR.* [2] [4] Wait for 1 byte to be received [3] [5] Check whether it is the (last receive - 1). [6] Read the receive data last. [4] [7] Set acknowledge of the final byte. Disable continuous reception (RCVD = 1). [8] Read the (final byte - 1) of receive data. [5] [9] Wait for the last byte to be receive. [6] [10] Clear the STOP flag. [11] Issue the stop condition. Set ACKBT in ICIER to 1 Set RCVD in ICCR1 to 1 Read ICDRR Read RDRF in ICSR No RDRF=1 ? [9] [8] [12] Wait for the creation of stop condition. [7] [13] Read the last byte of receive data. [14] Clear RCVD. [15] Set slave receive mode.
Yes Clear STOP in ICSR. Write 0 to BBSY and SCP Read STOP in ICSR No STOP=1 ? Yes Read ICDRR Clear RCVD in ICCR1 to 0 Clear MST in ICCR1 to 0 End
[10] [11]
[12]
[13] [14] [15]
Note: Do not activate an interrupt during the execution of steps [1] to [3]. Supplementary explanation: When one byte is received, steps [2] to [6] are skipped after step [1], before jumping to step [7]. The step [8] is dummy-read in ICDRR.
Figure 18.18 Sample Flowchart for Master Receive Mode
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Slave transmit mode Clear AAS in ICSR Write transmit data in ICDRT Read TDRE in ICSR No [3] TDRE=1 ? Yes No Last byte? Yes Write transmit data in ICDRT Read TEND in ICSR No [5] TEND=1 ? Yes Clear TEND in ICSR Clear TRS in ICCR1 to 0 Dummy read ICDRR Clear TDRE in ICSR End [4] [1]
[1] Clear the AAS flag. [2] Set transmit data for ICDRT (except for the last data). [3] Wait for ICDRT empty. [2] [4] Set the last byte of transmit data. [5] Wait for the last byte to be transmitted. [6] Clear the TEND flag . [7] Set slave receive mode. [8] Dummy-read ICDRR to release the SCL line. [9] Clear the TDRE flag.
[6] [7] [8] [9]
Figure 18.19 Sample Flowchart for Slave Transmit Mode
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Slave receive mode [1] Clear the AAS flag. Clear AAS in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR [1] [2] Set acknowledge to the transmit device. [2] [3] [3] Dummy-read ICDRR. [4] Wait for 1 byte to be received. [5] Check whether it is the (last receive - 1). Read RDRF in ICSR No RDRF=1 ? Yes Last receive - 1? No Read ICDRR Yes [8] Read the (last byte - 1) of receive data. [5] [9] Wait the last byte to be received. [6] [10] Read for the last byte of receive data. [4] [6] Read the receive data. [7] Set acknowledge of the last byte.
Set ACKBT in ICIER to 1
[7]
Read ICDRR Read RDRF in ICSR No
[8]
[9] RDRF=1 ? Yes Read ICDRR End [10]
Supplementary explanation: When one byte is received, steps [2] to [6] are skipped after step [1], before jumping to step [7]. The step [8] is dummy-read in ICDRR.
Figure 18.20 Sample Flowchart for Slave Receive Mode
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Section 18 I C Bus Interface 2 (IIC2)
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18.5
Interrupts
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost/overrun error. Table 18.3 shows the contents of each interrupt request. Table 18.3 Interrupt Requests
Clocked Synchronous 2 I C Mode Mode
Interrupt Request Transmit Data Empty Transmit End Receive Data Full STOP Recognition NACK Receive Arbitration Lost/Overrun Error
Abbreviation TXI TEI RXI STPI NAKI
Interrupt Condition (TDRE=1) * (TIE=1) (TEND=1) * (TEIE=1) (RDRF=1) * (RIE=1) (STOP=1) * (STIE=1) {(NACKF=1)+(AL=1)} * (NAKIE=1)
x x
When interrupt conditions described in table 18.3 are 1 and the I bit in CCR is 0, the CPU executes an interrupt exception processing. Interrupt sources should be cleared in the exception processing. TDRE and TEND are automatically cleared to 0 by writing the transmit data to ICDRT. RDRF are automatically cleared to 0 by reading ICDRR. TDRE is set to 1 again at the same time when transmit data is written to ICDRT. When TDRE is cleared to 0, then an excessive data of one byte may be transmitted.
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18.6
Bit Synchronous Circuit
In master mode, this module has a possibility that high level period may be short in the two states described below. * When SCL is driven to low by the slave device * When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 18.21 shows the timing of the bit synchronous circuit and table 18.4 shows the time when SCL output changes from low to Hi-Z then SCL is monitored.
SCL monitor timing reference clock SCL VIH
Internal SCL
Figure 18.21 Timing of Bit Synchronous Circuit Table 18.4 Time for Monitoring SCL
CKS3 0 CKS2 0 1 1 0 1 Time for Monitoring SCL 7.5 tcyc 19.5 tcyc 17.5 tcyc 41.5 tcyc
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2
18.7
18.7.1
Usage Notes
Issue (Retransmission) of Start/Stop Conditions
In master mode, when the start/stop conditions are issued (retransmitted) at the specific timing under the following condition 1 or 2, such conditions may not be output successfully. To avoid this, issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. Check the SCLO bit in the I2C control register 2 (IICR2) to confirm the fall of the ninth clock. 1. When the rising of SCL falls behind the time specified in section 18.6, Bit Synchronous Circuit, by the load of the SCL bus (load capacitance or pull-up resistance) 2. When the bit synchronous circuit is activated by extending the low period of eighth and ninth clocks, that is driven by the slave device 18.7.2 WAIT Setting in I2C Bus Mode Register (ICMR)
If the WAIT bit is set to 1, and the SCL signal is driven low for two or more transfer clocks by the slave device at the eighth and ninth clocks, the high period of ninth clock may be shortened. To avoid this, set the WAIT bit in ICMR to 0.
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2
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Section 19 A/D Converter
Section 19 A/D Converter
This LSI includes a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. The block diagram of the A/D converter is shown in figure 19.1.
19.1
* * * *
Features
* * *
*
10-bit resolution Eight input channels Conversion time: at least 3.5 s per channel (at 20-MHz operation) Two operating modes Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels Four data registers Conversion results are held in a data register for each channel Sample-and-hold function Two conversion start methods Software External trigger signal Interrupt source An A/D conversion end interrupt (ADI) request can be generated
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Section 19 A/D Converter
Module data bus
Internal data bus
AVCC 10-bit D/A
Successive approximations register
A D D R A
A D D R B
A D D R C
A D D R D
A D C S R
A D C R
AN0 AN2 AN3 AN4 AN5 AN6 AN7
Analog multiplexer
AN1
+ Control circuit Comparator Sample-andhold circuit
Bus interface
/4 /8 ADI interrupt
ADTRG [Legend] ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D
Figure 19.1 Block Diagram of A/D Converter
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Section 19 A/D Converter
19.2
Input/Output Pins
Table 19.1 summarizes the input pins used by the A/D converter. The 8 analog input pins are divided into two groups; analog input pins 0 to 3 (AN0 to AN3) comprising group 0, analog input pins 4 to 7 (AN4 to AN7) comprising group 1. The AVcc pin is the power supply pin for the analog block in the A/D converter. Table 19.1 Pin Configuration
Pin Name Analog power supply pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin Abbreviation AVCC AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG I/O Input Input Input Input Input Input Input Input Input Input External trigger input for starting A/D conversion Group 1 analog input Function Analog block power supply Group 0 analog input
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Section 19 A/D Converter
19.3
Register Descriptions
The A/D converter has the following registers. * * * * * * A/D data register A (ADDRA) A/D data register B (ADDRB) A/D data register C (ADDRC) A/D data register D (ADDRD) A/D control/status register (ADCSR) A/D control register (ADCR) A/D Data Registers A to D (ADDRA to ADDRD)
19.3.1
There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each analog input channel, are shown in table 19.2. The converted 10-bit data is stored in bits 15 to 6. The lower 6 bits are always read as 0. The data bus width between the CPU and the A/D converter is 8 bits. The upper byte can be read directly from the CPU, however the lower byte should be read via a temporary register. The temporary register contents are transferred from the ADDR when the upper byte data is read. Therefore, byte access to ADDR should be done by reading the upper byte first then the lower one. Word access is also possible. ADDR is initialized to H'0000. Table 19.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register to be Stored Results of A/D Conversion ADDRA ADDRB ADDRC ADDRD
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Section 19 A/D Converter
19.3.2
A/D Control/Status Register (ADCSR)
ADCSR consists of the control bits and conversion end status bits of the A/D converter.
Bit 7 Bit Name ADF Initial Value 0 R/W R/W Description A/D End Flag [Setting conditions] * * When A/D conversion ends in single mode When A/D conversion ends once on all the channels selected in scan mode
[Clearing condition] When 0 is written after reading ADF = 1 6 ADIE 0 R/W A/D Interrupt Enable A/D conversion end interrupt request (ADI) is enabled by ADF when this bit is set to 1 5 ADST 0 R/W A/D Start Setting this bit to 1 starts A/D conversion. In single mode, this bit is cleared to 0 automatically when conversion on the specified channel is complete. In scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to standby mode. 4 SCAN 0 R/W Scan Mode Selects single mode or scan mode as the A/D conversion operating mode. 0: Single mode 1: Scan mode 3 CKS 0 R/W Clock Select Selects the A/D conversions time. 0: Conversion time = 134 states (max.) 1: Conversion time = 70 states (max.) Clear the ADST bit to 0 before switching the conversion time.
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Section 19 A/D Converter
Bit 2 1 0
Bit Name CH2 CH1 CH0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Channel Select 2 to 0 Select analog input channels. When SCAN = 0 000: AN0 001: AN1 010: AN2 011: AN3 100: AN4 101: AN5 110: AN6 111: AN7 When SCAN = 1 000: AN0 001: AN0 and AN1 010: AN0 to AN2 011: AN0 to AN3 100: AN4 101: AN4 and AN5 110: AN4 to AN6 111: AN4 to AN7
19.3.3
A/D Control Register (ADCR)
ADCR enables A/D conversion started by an external trigger signal.
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Section 19 A/D Converter
Bit 7
Bit Name TRGE
Initial Value 0
R/W R/W
Description Trigger Enable A/D conversion is started at the falling edge and the rising edge of the external trigger signal (ADTRG) when this bit is set to 1. The selection between the falling edge and rising edge of the external trigger pin (ADTRG) conforms to the WPEG5 bit in the interrupt edge select register 2 (IEGR2)
6 to 4 3, 2
-- --
All 1 All 0
-- R/W
Reserved These bits are always read as 1. Reserved Although these bits are readable/writable, these bits should not be set to 1.
1 0
-- --
1 0
-- R/W
Reserved This bit is always read as 1. Reserved Although this bit is readable/writable, this bit should not be set to 1.
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Section 19 A/D Converter
19.4
Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST in ADCSR to 0. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 19.4.1 Single Mode
In single mode, A/D conversion is performed once for the analog input of the specified single channel as follows: 1. A/D conversion is started when the ADST bit in ADCSR is set to 1, according to software or external trigger input. 2. When A/D conversion is completed, the result is transferred to the corresponding A/D data register of the channel. 3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters the wait state. 19.4.2 Scan Mode
In scan mode, A/D conversion is performed sequentially for the analog input of the specified channels (four channels maximum) as follows: 1. When the ADST bit in ADCSR is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1). 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF flag in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt requested is generated. A/D conversion starts again on the first channel in the group. 4. The ADST bit is not automatically cleared to 0. Steps [2] and [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops.
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Section 19 A/D Converter
19.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then starts conversion. Figure 19.2 shows the A/D conversion timing. Table 19.3 shows the A/D conversion time. As indicated in figure 19.2, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 19.3. In scan mode, the values given in table 19.3 apply to the first conversion time. In the second and subsequent conversions, the conversion time is 128 states (fixed) when CKS = 0 and 66 states (fixed) when CKS = 1.
(1)
Address
(2)
Write signal
Input sampling timing ADF tD tSPL tCONV [Legend] ADCSR write cycle (1): ADCSR address (2): A/D conversion start delay time tD: Input sampling time tSPL: tCONV: A/D conversion time
Figure 19.2 A/D Conversion Timing
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Section 19 A/D Converter
Table 19.3 A/D Conversion Time (Single Mode)
CKS = 0 Item A/D conversion start delay time Input sampling time A/D conversion time Symbol tD tSPL tCONV Min. 6 -- 131 Typ. -- 31 -- Max. 9 -- 134 Min. 4 -- 69 CKS = 1 Typ. -- 15 -- Max. 5 -- 70
Note: All values represent the number of states.
19.4.4
External Trigger Input Timing
A/D conversion can also be started by an external trigger input. When the TRGE bit in ADCR is set to 1, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG input pin sets the ADST bit in ADCSR to 1, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 19.3 shows the timing.
ADTRG
Internal trigger signal
ADST A/D conversion
Figure 19.3 External Trigger Input Timing
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Section 19 A/D Converter
19.5
A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 19.4). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 19.5). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from 1111111110 to 1111111111 (see figure 19.5). * Nonlinearity error The deviation from the ideal A/D conversion characteristic as the voltage changes from zero to full scale. This does not include the offset error, full-scale error, or quantization error. * Absolute accuracy The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error.
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Section 19 A/D Converter
Digital output
Ideal A/D conversion characteristic 111
110
101
100
011
010
Quantization error
001
000
1 8
2 8
3 8
4 8
5 8
6 8
7 8
FS
Analog input voltage
Figure 19.4 A/D Conversion Accuracy Definitions (1)
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Section 19 A/D Converter
Digital output Full-scale error
Ideal A/D conversion characteristic
Nonlinearity error
Actual A/D conversion characteristic
FS Offset error Analog input voltage
Figure 19.4 A/D Conversion Accuracy Definitions (2)
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Section 19 A/D Converter
19.6
19.6.1
Usage Notes
Permissible Signal Source Impedance
This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k, charging may be insufficient and it may not be possible to guarantee A/D conversion accuracy. However, for A/D conversion in single mode with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 19.5). When converting a high-speed analog signal or converting in scan mode, a low-impedance buffer should be inserted. 19.6.2 Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND. Care is also required to ensure that filter circuits do not interfere with digital signals or act as antennas on the mounting board.
This LSI Sensor output impedance up to 5 k Sensor input Low-pass filter C to 0.1 F Cin = 15 pF
A/D converter equivalent circuit 10 k 20 pF
Figure 19.5 Analog Input Circuit Example
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Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional)
This LSI can include a power-on reset circuit and low-voltage detection circuit as optional circuits. The low-voltage detection circuit consists of two circuits: LVDI (interrupt by low voltage detect) and LVDR (reset by low voltage detect) circuits. This circuit is used to prevent abnormal operation (runaway execution) from occurring due to the power supply voltage fall and to recreate the state before the power supply voltage fall when the power supply voltage rises again. Even if the power supply voltage falls, the unstable state when the power supply voltage falls below the guaranteed operating voltage can be removed by entering standby mode when exceeding the guaranteed operating voltage and during normal operation. Thus, system stability can be improved. If the power supply voltage falls more, the reset state is automatically entered. If the power supply voltage rises again, the reset state is held for a specified period, then active mode is automatically entered. Figure 20.1 is a block diagram of the power-on reset circuit and the low-voltage detection circuit.
20.1
Features
* Power-on reset circuit Uses an external capacitor to generate an internal reset signal when power is first supplied. * Low-voltage detection circuit LVDR: Monitors the power-supply voltage, and generates an internal reset signal when the voltage falls below a specified value. LVDI: Monitors the power-supply voltage, and generates an interrupt when the voltage falls below or rises above respective specified values. Two pairs of detection levels for reset generation voltage are available: when only the LVDR circuit is used, or when the LVDI and LVDR circuits are both used.
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Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional)
CK R
OVF PSS R
RES
Noise canceler
Q S Power-on reset circuit
Internal reset signal
CRES
Noise canceler
Vreset Vcc Ladder resistor Vint
+ - + - LVDINT LVDRES Interrupt control circuit LVDSR
Reference voltage generator
Interrupt request Low-voltage detection circuit
[Legend] PSS: LVDCR: LVDSR: LVDRES: LVDINT: Vreset: Vint: Prescaler S Low-voltage-detection control register Low-voltage-detection status register Low-voltage-detection reset signal Low-voltage-detection interrupt signal Reset detection voltage Power-supply fall/rise detection voltage
Figure 20.1 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit
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Internal data bus
LVDCR
Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional)
20.2
Register Descriptions
The low-voltage detection circuit has the following registers. * Low-voltage-detection control register (LVDCR) * Low-voltage-detection status register (LVDSR) 20.2.1 Low-Voltage-Detection Control Register (LVDCR)
LVDCR is used to enable or disable the low-voltage detection circuit, set the detection levels for the LVDR function, enable or disable the LVDR function, and enable or disable generation of an interrupt when the power-supply voltage rises above or falls below the respective levels. Table 20.1 shows the relationship between the LVDCR settings and select functions. LVDCR should be set according to table 20.1.
Bit 7 Bit Name LVDE Initial Value 0* R/W R/W Description LVD Enable 0: The low-voltage detection circuit is not used (In standby mode) 1: The low-voltage detection circuit is used 6 to 4 All 1 Reserved These bits are always read as 1, and cannot be modified. 3 LVDSEL 0* R/W LVDR Detection Level Select 0: Reset detection voltage is 2.3 V (typ.) 1: Reset detection voltage is 3.6 V (typ.) When the falling or rising voltage detection interrupt is used, reset detection voltage of 2.3 V (typ.) should be used. When only a reset detection interrupt is used, reset detection voltage of 3.6 V (typ.) should be used. 2 LVDRE 0* R/W LVDR Enable 0: Disables the LVDR function 1: Enables the LVDR function
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Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Bit 1
Bit Name LVDDE
Initial Value 0
R/W R/W
Description Voltage-Fall-Interrupt Enable 0: Interrupt on the power-supply voltage falling below the selected detection level disabled 1: Interrupt on the power-supply voltage falling below the selected detection level enabled
0
LVDUE
0
R/W
Voltage-Rise-Interrupt Enable 0: Interrupt on the power-supply voltage rising above the selected detection level disabled 1: Interrupt on the power-supply voltage rising above the selected detection level enabled
Note:
*
Not initialized by LVDR but initialized by a power-on reset or WDT reset.
Table 20.1 LVDCR Settings and Select Functions
LVDCR Settings Select Functions
Low-VoltageDetection Falling Interrupt Low-VoltageDetection Rising Interrupt
LVDE
LVDSEL
LVDRE
LVDDE
LVDUE
Power-On Reset
LVDR
0 1 1 1 1 [Legend]
* 1 0 0 0
* 1 0 0 1 * means invalid.
* 0 1 1 1
* 0 0 1 1
O O O O O
O O
O O O
O O
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Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional)
20.2.2
Low-Voltage-Detection Status Register (LVDSR)
LVDSR indicates whether the power-supply voltage falls below or rises above the respective specified values.
Bit 7 to 2 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1, and cannot be modified. 1 LVDDF 0* R/W LVD Power-Supply Voltage Fall Flag [Setting condition] When the power-supply voltage falls below Vint (D) (typ. = 3.7 V) [Clearing condition] Writing 0 to this bit after reading it as 1 0 LVDUF 0* R/W LVD Power-Supply Voltage Rise Flag [Setting condition] When the power supply voltage falls below Vint (D) while the LVDUE bit in LVDCR is set to 1, then rises above Vint (U) (typ. = 4.0 V) before falling below Vreset1 (typ. = 2.3 V) [Clearing condition] Writing 0 to this bit after reading it as 1 Note: * Initialized by LVDR.
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Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional)
20.3
20.3.1
Operation
Power-On Reset Circuit
Figure 20.2 shows the timing of the operation of the power-on reset circuit. As the power-supply voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via the on-chip pull-up resistor (typ. 150 k). Since the state of the RES pin is transmitted within the chip, the prescaler S and the entire chip are in their reset states. When the level on the RES pin reaches the specified value, the prescaler S is released from its reset state and it starts counting. The OVF signal is generated to release the internal reset signal after the prescaler S has counted 131,072 clock () cycles. The noise cancellation circuit of approximately 100 ns is incorporated to prevent the incorrect operation of the chip by noise on the RES pin. To achieve stable operation of this LSI, the power supply needs to rise to its full level and settles within the specified time. The maximum time required for the power supply to rise and settle after power has been supplied (tPWON) is determined by the oscillation frequency (fOSC) and capacitance which is connected to RES pin (CRES). If tPWON means the time required to reach 90 % of power supply voltage, the power supply circuit should be designed to satisfy the following formula.
tPWON (ms) 90 x CRES (F) + 162/fOSC (MHz) (tPWON 3000 ms, CRES 0.22 F, and fOSC = 10 in 2-MHz to 10-MHz operation)
Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV and rise after charge on the RES pin is removed. To remove charge on the RES pin, it is recommended that the diode should be placed near Vcc. If the power supply voltage (Vcc) rises from the point above Vpor, a power-on reset may not occur.
tPWON Vcc Vpor RES Vss PSS-reset signal OVF Internal reset signal Vss
131,072 cycles
PSS counter starts
Reset released
Figure 20.2 Operational Timing of Power-On Reset Circuit
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Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional)
20.3.2
Low-Voltage Detection Circuit
Use this circuit in the system in which the power supply voltage Vcc is between 4.5 and 5.5 V. If so, the contents described in the section of electrical characteristics are guaranteed. LVDR (Reset by Low Voltage Detect) Circuit: Figure 20.3 shows the timing of the LVDR function. The LVDR enters the module-standby state after a power-on reset is canceled. To operate the LVDR, set the LVDE bit in LVDCR to 1, wait for 50 s (tLVDON) until the reference voltage and the low-voltage-detection power supply have stabilized by a software timer, etc., then set the LVDRE bit in LVDCR to 1. After that, the output settings of ports must be made. To cancel the low-voltage detection circuit, first the LVDRE bit should be cleared to 0 and then the LVDE bit should be cleared to 0. The LVDE and LVDRE bits must not be cleared to 0 simultaneously because incorrect operation may occur. When the power-supply voltage falls below the Vreset voltage (typ. = 2.3 V or 3.6 V), the LVDR clears the LVDRES signal to 0, and resets the prescaler S. The low-voltage detection reset state remains in place until a power-on reset is generated. When the power-supply voltage rises above the Vreset voltage again, the prescaler S starts counting. It counts 131,072 clock () cycles, and then releases the internal reset signal. In this case, the LVDE, LVDSEL, and LVDRE bits in LVDCR are not initialized. Note that if the power supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises from that point, the low-voltage detection reset may not occur. If the power supply voltage (Vcc) falls below Vpor = 100 mV, a power-on reset occurs.
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Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional)
VCC
Vreset
VLVDRmin VSS LVDRES PSS-reset signal OVF
Internal reset signal
131,072 cycles PSS counter starts Reset released
Figure 20.3 Operational Timing of LVDR Circuit LVDI (Interrupt by Low Voltage Detect) Circuit: Figure 20.4 shows the timing of LVDI functions. The LVDI enters the module-standby state after a power-on reset is canceled. To operate the LVDI, set the LVDE bit in LVDCR to 1, wait for 50 s (tLVDON) until the reference voltage and the low-voltage-detection power supply have stabilized by a software timer, etc., then set the LVDDE and LVDUE bits in LVDCR to 1. After that, the output settings of ports must be made. To cancel the low-voltage detection circuit, first the LVDDE and LVDUE bits should all be cleared to 0 and then the LVDE bit should be cleared to 0. The LVDE bit must not be cleared to 0 at the same timing as the LVDDE and LVDUE bits because incorrect operation may occur. When the power-supply voltage falls below Vint (D) (typ. = 3.7 V) voltage, the LVDI clears the LVDINT signal to 0 and the LVDDF bit in LVDSR is set to 1. If the LVDDE bit is 1 at this time, an IRQ0 interrupt request is simultaneously generated. In this case, the necessary data must be saved in the external EEPROM, etc, and a transition must be made to standby mode or subsleep mode. Until this processing is completed, the power supply voltage must be higher than the lower limit of the guaranteed operating voltage. When the power-supply voltage does not fall below Vreset1 (typ. = 2.3 V) voltage but rises above Vint (U) (typ. = 4.0 V) voltage, the LVDI sets the LVDINT signal to 1. If the LVDUE bit is 1 at this time, the LVDUF bit in LVDSR is set to 1 and an IRQ0 interrupt request is simultaneously generated.
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Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional)
If the power supply voltage (Vcc) falls below Vreset1 (typ. = 2.3 V) voltage, the LVDR function is performed.
Vcc
Vint (U) Vint (D) Vreset1 VSS
LVDINT LVDDE LVDDF LVDUE LVDUF IRQ0 interrupt generated IRQ0 interrupt generated
Figure 20.4 Operational Timing of LVDI Circuit Procedures for Clearing Settings when Using LVDR and LVDI: To operate or release the low-voltage detection circuit normally, follow the procedure described below. Figure 20.5 shows the timing for the operation and release of the low-voltage detection circuit. 1. To operate the low-voltage detection circuit, set the LVDE bit in LVDCR to 1. 2. Wait for 50 s (tLVDON) until the reference voltage and the low-voltage-detection power supply have stabilized by a software timer, etc. Then, clear the LVDDF and LVDUF bits in LVDSR to 0 and set the LVDRE, LVDDE, and LVDUE bits in LVDCR to 1, as required. 3. To release the low-voltage detection circuit, start by clearing all of the LVDRE, LVDDE, and LVDUE bits to 0. Then clear the LVDE bit to 0. The LVDE bit must not be cleared to 0 at the same timing as the LVDRE, LVDDE, and LVDUE bits because incorrect operation may occur.
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Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional)
LVDE
LVDRE
LVDDE
LVDUE tLVDON
Figure 20.5 Timing for Operation/Release of Low-Voltage Detection Circuit
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Section 21 Power Supply Circuit
Section 21 Power Supply Circuit
This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external VCC pin. As a result, the current consumed when an external power supply is used at 3.0 V or above can be held down to virtually the same low level as when used at approximately 3.0 V. If the external power supply is 3.0 V or below, the internal voltage will be practically the same as the external voltage. It is, of course, also possible to use the same level of external power supply voltage and internal power supply voltage without using the internal power supply step-down circuit.
21.1
When Using Internal Power Supply Step-Down Circuit
Connect the external power supply to the VCC pin, and connect a capacitance of approximately 0.1 F between VCL and VSS, as shown in figure 21.1. The internal step-down circuit is made effective simply by adding this external circuit. In the external circuit interface, the external power supply voltage connected to VCC and the GND potential connected to VSS are the reference levels. For example, for port input/output levels, the VCC level is the reference for the high level, and the VSS level is that for the low level. The A/D converter analog power supply is not affected by the internal step-down circuit.
VCC VCC = 3.0 to 5.5 V
Step-down circuit
VCL
Internal logic
Internal power supply VSS
Stabilization capacitance (approx. 0.1 F)
Figure 21.1 Power Supply Connection when Internal Step-Down Circuit is Used
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Section 21 Power Supply Circuit
21.2
When Not Using Internal Power Supply Step-Down Circuit
When the internal power supply step-down circuit is not used, connect the external power supply to the VCL pin and VCC pin, as shown in figure 21.2. The external power supply is then input directly to the internal power supply. The permissible range for the power supply voltage is 3.0 V to 3.6 V. Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more than 3.6 V) is input.
VCC VCC = 3.0 to 3.6 V
Step-down circuit
VCL
Internal logic
Internal power supply VSS
Figure 21.2 Power Supply Connection when Internal Step-Down Circuit is Not Used
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Section 22 List of Registers
Section 22 List of Registers
The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register addresses (address order) * Registers are listed from the lower allocation addresses. * The symbol in the register-name column represents a reserved address or range of reserved addresses. Do not attempt to access reserved addresses. * When the address is 16-bit wide, the address of the upper byte is given in the list. * Registers are classified by functional modules. * The data bus width is indicated. 2. * * * Register bits Bit configurations of the registers are described in the same order as the register addresses. Reserved bits are indicated by in the bit name column. No entry in the bit-name column indicates that the whole register is allocated as a counter or for holding data. * When registers consist of 16 bits, bits are described from the MSB side. 3. Register states in each operating mode * Register states are described in the same order as the register addresses. * The register states described here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
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Section 22 List of Registers
22.1
Register Addresses (Address Order)
The data-bus width column indicates the number of bits. The access-state column shows the number of states of the specified basic clock that is required for access to the register. Note: Access to undefined or reserved addresses is prohibited. Correct operation of the access itself or later operations is not guaranteed when such a register is accessed.
Abbreviation -- SMR_3 BRR_3 Module Name -- SCI3_3 SCI3_3 SCI3_3 SCI3_3 SCI3_3 SCI3_3 -- SCI3_3 -- Timer Z0 Timer Z0 Timer Z0 Timer Z0 Timer Z0 Timer Z0 Timer Z0 Timer Z0 Timer Z0 Timer Z0 Timer Z0 Data Bus Width -- 8 8 8 8 8 8 -- 8 -- 8 8 8 8 8 8 16 16 16 16 16 Access State -- 3 3 3 3 3 3 -- 3 -- 2 2 2 2 2 2 2 2 2 2 2
Register Name -- Serial mode register_3 Bit rate register_3 Serial control register 3_3 Transmit data register_3 Serial status register_3 Receive data register_3 -- Serial mode control register -- Timer control register_0 Timer I/O control register A_0 Timer I/O control register C_0 Timer status register_0
Bit No. Address -- 8 8 H'FFF000 to H'FFF5FF H'FFF600 H'FFF601 H'FFF602 H'FFF603 H'FFF604 H'FFF605 H'FFF606, H'FFF607 H'FFF608 H'FFF609 to H'FFF6FF H'FFF700 H'FFF701 H'FFF702 H'FFF703 H'FFF704 H'FFF705 H'FFF706 H'FFF708 H'FFF70A H'FFF70C H'FFF70E
SCR3_3 8 TDR_3 SSR_3 RDR_3 -- 8 8 8 --
SMCR_3 8 -- TCR_0 -- 8
TIORA_0 8 TIORC_0 8 TSR_0 8 8
Timer interrupt enable register_0 TIER_0 PWM mode output level control register_0 Timer counter_0 General register A_0 General register B_0 General register C_0 General register D_0
POCR_0 8 TCNT_0 16 GRA_0 GRB_0 GRC_0 GRD_0 16 16 16 16
Rev. 3.00 Mar. 15, 2006 Page 404 of 526 REJ09B0060-0300
Section 22 List of Registers
Register Name Timer control register_1 Timer I/O control register A_1 Timer I/O control register C_1 Timer status register_1 Timer interrupt enable register_1
Abbreviation TCR_1
Bit No. Address 8 H'FFF710 H'FFF711 H'FFF712 H'FFF713 H'FFF714 H'FFF715 H'FFF716 H'FFF718 H'FFF71A H'FFF71C H'FFF71E H'FFF720 H'FFF721 H'FFF722 H'FFF723 H'FFF724 H'FFF725 H'FFF726, H'FFF727 H'FFF728 H'FFF729 H'FFF72A H'FFF72B H'FFF72C
Module Name Timer Z1 Timer Z1 Timer Z1 Timer Z1 Timer Z1 Timer Z1 Timer Z1 Timer Z1 Timer Z1 Timer Z1 Timer Z1 Timer Z common Timer Z common Timer Z common Timer Z common Timer Z common Timer Z common -- RTC RTC RTC RTC RTC
Data Bus Width 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 8 -- 8 8 8 8 8
Access State 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -- 2 2 2 2 2
TIORA_1 8 TIORC_1 8 TSR_1 TIER_1 8 8 8 16 16 16 16 16 8 8 8 8 8 8 --
PWM mode output level control POCR_1 register_1 Timer counter_1 General register A_1 General register B_1 General register C_1 General register D_1 Timer start register Timer mode register Timer PWM mode register Timer function control register Timer output master enable register Timer output control register -- Second data register/free running counter data register Minute data register Hour data register Day-of-week data register RTC control register 1 TCNT_1 GRA_1 GRB_1 GRC_1 GRD_1 TSTR TMDR TPMR TFCR TOER TOCR --
RSECDR 8 RMINDR RHRDR RWKDR RTCCR1 8 8 8 8
Rev. 3.00 Mar. 15, 2006 Page 405 of 526 REJ09B0060-0300
Section 22 List of Registers
Register Name RTC control register 2 -- Clock source select register Low-voltage-detection control register Low-voltage-detection status register -- Serial mode register_2 Bit rate register_2 Serial control register 3_2 Transmit data register_2 Serial status register_2 Receive data register_2 -- I2C bus control register 1 I C bus control register 2 I2C bus mode register
2 2 2
Abbreviation RTCCR2 -- RTCCSR LVDCR LVDSR -- SMR_2 BRR_2 SCR3_2 TDR_2 SSR_2 RDR_2 -- ICCR1 ICCR2 ICMR
Bit No. Address 8 -- 8 8 8 -- 8 8 8 8 8 8 -- 8 8 8 8 8 8 8 8 -- 8 8 8 -- H'FFF72D H'FFF72E H'FFF72F H'FFF730 H'FFF731 H'FFF732 to H'FFF73F H'FFF740 H'FFF741 H'FFF742 H'FFF743 H'FFF744 H'FFF745 H'FFF746, H'FFF747 H'FFF748 H'FFF749 H'FFF74A H'FFF74B H'FFF74C H'FFF74D H'FFF74E H'FFF74F H'FFF750 to H'FFF75F H'FFF760 H'FFF761 H'FFF761 H'FFF762 to H'FFFF7F
Module Name RTC -- RTC LVDC*
1
Data Bus Width 8 -- 8 8 8 -- 8 8 8 8 8 8 -- 8 8 8 8 8 8 8 8 -- 8 8 8 --
Access State 2 -- 2 2 2 -- 3 3 3 3 3 3 -- 2 2 2 2 2 2 2 2 -- 2 2 2 --
LVDC*1 -- SCI3_2 SCI3_2 SCI3_2 SCI3_2 SCI3_2 SCI3_2 -- IIC2 IIC2 IIC2 IIC2 IIC2 IIC2 IIC2 IIC2 -- Timer B1 Timer B1 Timer B1 --
I C bus interrupt enable register ICIER I C bus status register Slave address register I C bus transmit data register I C bus receive data register -- Timer mode register B1 Timer counter B1 Timer load register B1 --
2 2
ICSR SAR ICDRT ICDRR -- TMB1 TCB1 TLB1 --
Rev. 3.00 Mar. 15, 2006 Page 406 of 526 REJ09B0060-0300
Section 22 List of Registers
Register Name Timer mode register W Timer control register W
Timer interrupt enable register W
Abbreviation TMRW TCRW TIERW TSRW TIOR0 TIOR1 TCNT GRA GRB GRC GRD FLMCR1 FLMCR2
Bit No. Address 8 8 8 8 8 8 16 16 16 16 16 8 8 H'FFFF80 H'FFFF81 H'FFFF82 H'FFFF83 H'FFFF84 H'FFFF85 H'FFFF86 H'FFFF88 H'FFFF8A H'FFFF8C H'FFFF8E H'FFFF90 H'FFFF91 H'FFFF92 H'FFFF93
Module Name Timer W Timer W Timer W Timer W Timer W Timer W Timer W Timer W Timer W Timer W Timer W ROM ROM ROM ROM
Data Bus Width 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 -- 8 --
Access State 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -- 2 --
Timer status register W Timer I/O control register 0 Timer I/O control register 1 Timer counter General register A General register B General register C General register D Flash memory control register 1 Flash memory control register 2 Flash memory power control register Erase block register 1 -- Flash memory enable register --
FLPWCR 8 EBR1 -- FENR -- 8 -- 8 --
H'FFFF94 to -- H'FFFF9A H'FFFF9B H'FFFF9C to H'FFFF9F H'FFFFA0 H'FFFFA1 H'FFFFA2 H'FFFFA3 H'FFFFA4 H'FFFFA5 H'FFFFA6, H'FFFFA7 H'FFFFA8 H'FFFFA9 ROM --
Timer control register V0 Timer control/status register V Time constant register A Time constant register B Timer counter V Timer control register V1 -- Serial mode register Bit rate register
TCRV0 TCSRV TCORA TCORB TCNTV TCRV1 -- SMR BRR
8 8 8 8 8 8 -- 8 8
Timer V Timer V Timer V Timer V Timer V Timer V -- SCI3 SCI3
8 8 8 8 8 8 -- 8 8
3 3 3 3 3 3 -- 3 3
Rev. 3.00 Mar. 15, 2006 Page 407 of 526 REJ09B0060-0300
Section 22 List of Registers
Register Name Serial control register 3 Transmit data register Serial status register Receive data register -- A/D data register A A/D data register B A/D data register C A/D data register D A/D control/status register A/D control register -- PWM data register L PWM data register U PWM control register -- Timer control/status register WD Timer counter WD Timer mode register WD -- --
Abbreviation SCR3 TDR SSR RDR -- ADDRA ADDRB ADDRC ADDRD ADCSR ADCR -- PWDRL PWDRU PWCR --
Bit No. Address 8 8 8 8 -- 16 16 16 16 8 8 -- 8 8 8 -- H'FFFFAA H'FFFFAB H'FFFFAC H'FFFFAD H'FFFFAE, H'FFFFAF H'FFFFB0 H'FFFFB2 H'FFFFB4 H'FFFFB6 H'FFFFB8 H'FFFFB9 H'FFFFBA, H'FFFFBB H'FFFFBC H'FFFFBD H'FFFFBE H'FFFFBF H'FFFFC0 H'FFFFC1 H'FFFFC2 H'FFFFC3 H'FFFFC4 to H'FFFFC7
Module Name SCI3 SCI3 SCI3 SCI3 --
Data Bus Width 8 8 8 8 --
Access State 3 3 3 3 -- 3 3 3 3 3 3 -- 2 2 2 -- 2 2 2 -- --
A/D 8 converter A/D 8 converter A/D 8 converter A/D 8 converter A/D 8 converter A/D 8 converter -- 14-bit PWM 14-bit PWM 14-bit PWM -- WDT*
2
-- 8 8 8 -- 8 8 8 -- --
TCSRWD 8 TCWD TMWD -- -- 8 8 -- --
WDT*2 WDT* -- --
2
Rev. 3.00 Mar. 15, 2006 Page 408 of 526 REJ09B0060-0300
Section 22 List of Registers
Register Name Address break control register Address break status register Break address register H Break address register L Break data register H Break data register L -- Break address register E Port pull-up control register 1 Port pull-up control register 5 -- Port data register 1 Port data register 2 Port data register 3 -- Port data register 5 Port data register 6 Port data register 7 Port data register 8 Port data register 9 Port data register B -- Port mode register 1 Port mode register 5
Abbreviation ABRKCR ABRKSR BARH BARL BDRH BDRL -- BARE PUCR1 PUCR5 -- PDR1 PDR2 PDR3 -- PDR5 PDR6 PDR7 PDR8 PDR9 PDRB -- PMR1 PMR5
Bit No. Address 8 8 8 8 8 8 -- 8 8 8 -- 8 8 8 -- 8 8 8 8 8 8 -- 8 8 H'FFFFC8 H'FFFFC9 H'FFFFCA H'FFFFCB H'FFFFCC H'FFFFCD H'FFFFCE H'FFFFCF H'FFFFD0 H'FFFFD1 H'FFFFD2, H'FFFFD3 H'FFFFD4 H'FFFFD5 H'FFFFD6 H'FFFFD7 H'FFFFD8 H'FFFFD9 H'FFFFDA H'FFFFDB H'FFFFDC H'FFFFDD
Module Name Address break Address break Address break Address break Address break Address break -- Address break I/O port I/O port -- I/O port I/O port I/O port -- I/O port I/O port I/O port I/O port I/O port I/O port
Data Bus Width 8 8 8 8 8 8 -- 8 8 8 -- 8 8 8 -- 8 8 8 8 8 8 -- 8 8
Access State 2 2 2 2 2 2 -- 2 2 2 -- 2 2 2 -- 2 2 2 2 2 2 -- 2 2
H'FFFFDE, -- H'FFFFDF H'FFFFE0 H'FFFFE1 I/O port I/O port
Rev. 3.00 Mar. 15, 2006 Page 409 of 526 REJ09B0060-0300
Section 22 List of Registers
Register Name Port mode register 3 -- Port control register 1 Port control register 2 Port control register 3 -- Port control register 5 Port control register 6 Port control register 7 Port control register 8 Port control register 9 --
Abbreviation PMR3 -- PCR1 PCR2 PCR3 -- PCR5 PCR6 PCR7 PCR8 PCR9 --
Bit No. Address 8 -- 8 8 8 -- 8 8 8 8 8 -- H'FFFFE2 H'FFFFE3 H'FFFFE4 H'FFFFE5 H'FFFFE6 H'FFFFE7 H'FFFFE8 H'FFFFE9 H'FFFFEA H'FFFFEB H'FFFFEC H'FFFFED to H'FFFFEF H'FFFFF0 H'FFFFF1 H'FFFFF2 H'FFFFF3 H'FFFFF4 H'FFFFF5 H'FFFFF6 H'FFFFF7 H'FFFFF8 H'FFFFF9 H'FFFFFA H'FFFFFB to H'FFFFFF
Module Name I/O port -- I/O port I/O port I/O port -- I/O port I/O port I/O port I/O port I/O port --
Data Bus Width 8 -- 8 8 8 -- 8 8 8 8 8 --
Access State 2 -- 2 2 2 -- 2 2 2 2 2 --
System control register 1 System control register 2 Interrupt edge select register 1 Interrupt edge select register 2 Interrupt enable register 1 Interrupt enable register 2 Interrupt flag register 1 Interrupt flag register 2 Wakeup interrupt flag register
SYSCR1 SYSCR2 IEGR1 IEGR2 IENR1 IENR2 IRR1 IRR2 IWPR
8 8 8 8 8 8 8 8 8 8 8 --
Powerdown Powerdown Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Powerdown Powerdown --
8 8 8 8 8 8 8 8 8 8 8 --
2 2 2 2 2 2 2 2 2 2 2 --
Module standby control register 1 MSTCR1 Module standby control register 2 MSTCR2 -- --
Notes: 1. LVDC: Low-voltage detection circuits (optional) 2. WDT: Watchdog timer
Rev. 3.00 Mar. 15, 2006 Page 410 of 526 REJ09B0060-0300
Section 22 List of Registers
22.2
Register Bits
The addresses and bit names of the registers in the on-chip peripheral modules are listed below. The 16-bit register is indicated in two rows, 8 bits for each row.
Register Name SMR_3 BRR_3 SCR3_3 TDR_3 SSR_3 RDR_3 SMCR_3 TCR_0 TIORA_0 TIORC_0 TSR_0 TIER_0 POCR_0 TCNT_0 Bit 7 COM BRR7 TIE TDR7 TDRE RDR7 -- CCLR2 -- -- -- -- -- Bit 6 CHR BRR6 RIE TDR6 RDRF RDR6 -- CCLR1 IOB2 IOD2 -- -- -- Bit 5 PE BRR5 TE TDR5 OER RDR5 -- CCLR0 IOB1 IOD1 -- -- -- Bit 4 PM BRR4 RE TDR4 FER RDR4 -- CKEG1 IOB0 IOD0 OVF OVIE -- Bit 3 STOP BRR3 MPIE TDR3 PER RDR3 -- CKEG0 -- -- IMFD IMIED -- Bit 2 MP BRR2 TEIE TDR2 TEND RDR2 NFEN_3 TPSC2 IOA2 IOC2 IMFC IMIEC POLD Bit 1 CKS1 BRR1 CKE1 TDR1 MPBR RDR1 TXD_3 TPSC1 IOA1 IOC1 IMFB IMIEB POLC Bit 0 CKS0 BRR0 CKE0 TDR0 MPBT RDR0 MSTS3_3 TPSC0 IOA0 IOC0 IMFA IMIEA POLB Timer Z0 Module Name SCI3_3
TCNT0H7 TCNT0H6 TCNT0H5 TCNT0H4 TCNT0H3 TCNT0H2 TCNT0H1 TCNT0H0 TCNT0L7 TCNT0L6 GRA0H6 GRA0L6 GRB0H6 GRB0L6 GRC0H6 GRC0L6 GRD0H6 GRD0L6 CCLR1 IOB2 IOD2 TCNT0L5 GRA0H5 GRA0L5 GRB0H5 GRB0L5 GRC0H5 GRC0L5 GRD0H5 GRD0L5 CCLR0 IOB1 IOD1 TCNT0L4 GRA0H4 GRA0L4 GRB0H4 GRB0L4 GRC0H4 GRC0L4 GRD0H4 GRD0L4 CKEG1 IOB0 IOD0 TCNT0L3 GRA0H3 GRA0L3 GRB0H3 GRB0L3 GRC0H3 GRC0L3 GRD0H3 GRD0L3 CKEG0 -- -- TCNT0L2 GRA0H2 GRA0L2 GRB0H2 GRB0L2 GRC0H2 GRC0L2 GRD0H2 GRD0L2 TPSC2 IOA2 IOC2 TCNT0L1 GRA0H1 GRA0L1 GRB0H1 GRB0L1 GRC0H1 GRC0L1 GRD0H1 GRD0L1 TPSC1 IOA1 IOC1 TCNT0L0 GRA0H0 GRA0L0 GRB0H0 GRB0L0 GRC0H0 GRC0L0 GRD0H0 GRD0L0 TPSC0 IOA0 IOC0 Timer Z1
GRA_0
GRA0H7 GRA0L7
GRB_0
GRB0H7 GRB0L7
GRC_0
GRC0H7 GRC0L7
GRD_0
GRD0H7 GRD0L7
TCR_1 TIORA_1 TIORC_1
CCLR2 -- --
Rev. 3.00 Mar. 15, 2006 Page 411 of 526 REJ09B0060-0300
Section 22 List of Registers
Register Name TSR_1 TIER_1 POCR_1 TCNT_1 Bit 7 -- -- -- Bit 6 -- -- -- Bit 5 UDF -- -- Bit 4 OVF OVIE -- Bit 3 IMFD IMIED -- Bit 2 IMFC IMIEC POLD Bit 1 IMFB IMIEB POLC Bit 0 IMFA IMIEA POLB
Module Name Timer Z1
TCNT1H7 TCNT1H6 TCNT1H5 TCNT1H4 TCNT1H3 TCNT1H2 TCNT1H1 TCNT1H0 TCNT1L7 TCNT1L6 GRA1H6 GRA1L6 GRB1H6 GRB1L6 GRC1H6 GRC1L6 GRD1H6 GRD1L6 -- BFC1 PWMD1 STCLK EC1 TOC1 SC12 MN12 -- -- 12/24 -- RCS6 -- -- TCNT1L5 GRA1H5 GRA1L5 GRB1H5 GRB1L5 GRC1H5 GRC1L5 GRD1H5 GRD1L5 -- BFD0 PWMC1 ADEG EB1 TOB1 SC11 MN11 HR11 -- PM FOIE RCS5 -- -- TCNT1L4 GRA1H4 GRA1L4 GRB1H4 GRB1L4 GRC1H4 GRC1L4 GRD1H4 GRD1L4 -- BFC0 PWMB1 ADTRG EA1 TOA1 SC10 MN10 HR10 -- RST WKIE -- -- -- TCNT1L3 GRA1H3 GRA1L3 GRB1H3 GRB1L3 GRC1H3 GRC1L3 GRD1H3 GRD1L3 -- -- -- OLS1 ED0 TOD0 SC03 MN03 HR03 -- INT DYIE RCS3 LVDSEL -- TCNT1L2 GRA1H2 GRA1L2 GRB1H2 GRB1L2 GRC1H2 GRC1L2 GRD1H2 GRD1L2 -- -- PWMD0 OLS0 EC0 TOC0 SC02 MN02 HR02 WK2 -- HRIE RCS2 LVDRE -- TCNT1L1 GRA1H1 GRA1L1 GRB1H1 GRB1L1 GRC1H1 GRC1L1 GRD1H1 GRD1L1 STR1 -- PWMC0 CMD1 EB0 TOB0 SC01 MN01 HR01 WK1 -- MNIE RCS1 LVDDE LVDDF TCNT1L0 GRA1H0 GRA1L0 GRB1H0 GRB1L0 GRC1H0 GRC1L0 GRD1H0 GRD1L0 STR0 SYNC PWMB0 CMD0 EA0 TOA0 SC00 MN00 HR00 WK0 -- SEIE RCS0 LVDUE LVDUF LVDC 1 (optional)* RTC Timer Z common
GRA_1
GRA1H7 GRA1L7
GRB_1
GRB1H7 GRB1L7
GRC_1
GRC1H7 GRC1L7
GRD_1
GRD1H7 GRD1L7
TSTR TMDR TPMR TFCR TOER TOCR RSECDR RMINDR RHRDR RWKDR RTCCR1 RTCCR2 RTCCSR LVDCR LVDSR
-- BFD1 -- -- ED1 TOD1 BSY BSY BSY BSY RUN -- -- LVDE --
Rev. 3.00 Mar. 15, 2006 Page 412 of 526 REJ09B0060-0300
Section 22 List of Registers
Register Name SMR_2 BRR_2 SCR3_2 TDR_2 SSR_2 RDR_2 ICCR1 ICCR2 ICMR ICIER ICSR SAR ICDRT ICDRR TMB1 TCB1 TLB1 TMRW TCRW TIERW TSRW TIOR0 TIOR1 TCNT Bit 7 COM BRR7 TIE TDR7 TDRE RDR7 ICE BBSY MLS TIE TDRE SVA6 ICDRT7 ICDRR7 TMB17 TCB17 TLB17 CTS CCLR OVIE OVF -- -- TCNT15 TCNT7 GRA GRA15 GRA7 GRB GRB15 GRB7 GRC GRC15 GRC7 Bit 6 CHR BRR6 RIE TDR6 RDRF RDR6 RCVD SCP WAIT TEIE TEND SVA5 ICDRT6 ICDRR6 -- TCB16 TLB16 -- CKS2 -- -- IOB2 IOD2 TCNT14 TCNT6 GRA14 GRA6 GRB14 GRB6 GRC14 GRC6 Bit 5 PE BRR5 TE TDR5 OER RDR5 MST SDAO -- RIE RDRF SVA4 ICDRT5 ICDRR5 -- TCB15 TLB15 BUFEB CKS1 -- -- IOB1 IOD1 TCNT13 TCNT5 GRA13 GRA5 GRB13 GRB5 GRC13 GRC5 Bit 4 PM BRR4 RE TDR4 FER RDR4 TRS SDAOP -- NAKIE NACKF SVA3 ICDRT4 ICDRR4 -- TCB14 TLB14 BUFEA CKS0 -- -- IOB0 IOD0 TCNT12 TCNT4 GRA12 GRA4 GRB12 GRB4 GRC12 GRC4 Bit 3 STOP BRR3 MPIE TDR3 PER RDR3 CKS3 SCLO BCWP STIE STOP SVA2 ICDRT3 ICDRR3 -- TCB13 TLB13 -- TOD IMIED IMFD -- -- TCNT11 TCNT3 GRA11 GRA3 GRB11 GRB3 GRC11 GRC3 Bit 2 MP BRR2 TEIE TDR2 TEND RDR2 CKS2 -- BC2 ACKE AL/OVE SVA1 ICDRT2 ICDRR2 TMB12 TCB12 TLB12 PWMD TOC IMIEC IMFC IOA2 IOC2 TCNT10 TCNT2 GRA10 GRA2 GRB10 GRB2 GRC10 GRC2 Bit 1 CKS1 BRR1 CKE1 TDR1 MPBR RDR1 CKS1 IICRST BC1 ACKBR AAS SVA0 ICDRT1 ICDRR1 TMB11 TCB11 TLB11 PWMC TOB IMIEB IMFB IOA1 IOC1 TCNT9 TCNT1 GRA9 GRA1 GRB9 GRB1 GRC9 GRC1 Bit 0 CKS0 BRR0 CKE0 TDR0 MPBT RDR0 CKS0 -- BC0 ACKBT ADZ FS ICDRT0 ICDRR0 TMB10 TCB10 TLB10 PWMB TOA IMIEA IMFA IOA0 IOC0 TCNT8 TCNT0 GRA8 GRA0 GRB8 GRB0 GRC8 GRC0
Module Name SCI3_2
IIC2
Timer B1
Timer W
Rev. 3.00 Mar. 15, 2006 Page 413 of 526 REJ09B0060-0300
Section 22 List of Registers
Register Name GRD Bit 7 GRD15 GRD7 FLMCR1 FLMCR2 FLPWCR EBR1 FENR TCRV0 TCSRV TCORA TCORB TCNTV TCRV1 SMR BRR SCR3 TDR SSR RDR ADDRA -- FLER PDWND EB7 FLSHE CMIEB CMFB TCORA7 TCORB7 TCNTV7 -- COM BRR7 TIE TDR7 TDRE RDR7 AD9 Bit 6 GRD14 GRD6 SWE -- -- EB6 -- CMIEA CFMA TCORA6 TCORB6 TCNTV6 -- CHR BRR6 RIE TDR6 RDRF RDR6 AD8 Bit 5 GRD13 GRD5 ESU -- -- EB5 -- OVIE OVF TCORA5 TCORB5 TCNTV5 -- PE BRR5 TE TDR5 OER RDR5 AD7 Bit 4 GRD12 GRD4 PSU -- -- EB4 -- CCLR1 -- TCORA4 TCORB4 TCNTV4 TVEG1 PM BRR4 RE TDR4 FER RDR4 AD6 Bit 3 GRD11 GRD3 EV -- -- EB3 -- CCLR0 OS3 TCORA3 TCORB3 TCNTV3 TVEG0 STOP BRR3 MPIE TDR3 PER RDR3 AD5 Bit 2 GRD10 GRD2 PV -- -- EB2 -- CKS2 OS2 TCORA2 TCORB2 TCNTV2 TRGE MP BRR2 TEIE TDR2 TEND RDR2 AD4 Bit 1 GRD9 GRD1 E -- -- EB1 -- CKS1 OS1 TCORA1 TCORB1 TCNTV1 -- CKS1 BRR1 CKE1 TDR1 MPBR RDR1 AD3 Bit 0 GRD8 GRD0 P -- -- EB0 -- CKS0 OS0 TCORA0 TCORB0 TCNTV0 ICKS0 CKS0 BRR0 CKE0 TDR0 MPBT RDR0 AD2
Module Name Timer W
ROM
Timer V
SCI3
A/D converter
AD1 ADDRB AD9 AD1 ADDRC AD9 AD1 ADDRD AD9 AD1 ADCSR ADCR ADF TRGE
AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE --
-- AD7 -- AD7 -- AD7 -- ADST --
-- AD6 -- AD6 -- AD6 -- SCAN --
-- AD5 -- AD5 -- AD5 -- CKS --
-- AD4 -- AD4 -- AD4 -- CH2 --
-- AD3 -- AD3 -- AD3 -- CH1 --
-- AD2 -- AD2 -- AD2 -- CH0 --
Rev. 3.00 Mar. 15, 2006 Page 414 of 526 REJ09B0060-0300
Section 22 List of Registers
Register Name PWDRL PWDRU PWCR TCSRWD TCWD TMWD ABRKCR ABRKSR BARH BARL BDRH BDRL BARE PUCR1 PUCR5 PDR1 PDR2 PDR3 PDR5 PDR6 PDR7 PDR8 PDR9 PDRB PMR1 PMR5 PMR3 PCR1 PCR2 PCR3 PCR5 Bit 7 PWDRL7 -- -- B6WI TCWD7 -- RTINTE ABIF BARH7 BARL7 BDRH7 BDRL7 BARE7 PUCR17 -- P17 -- P37 P57 P67 P77 P87 P97 PB7 IRQ3 POF57 -- PCR17 -- PCR37 PCR57 Bit 6 PWDRL6 -- -- TCWE TCWD6 -- CSEL1 ABIE BARH6 BARL6 BDRH6 BDRL6 BARE6 PUCR16 -- P16 -- P36 P56 P66 P76 P86 P96 PB6 IRQ2 POF56 -- PCR16 -- PCR36 PCR56 Bit 5 PWDRL5 PWDRU5 -- B4WI TCWD5 -- CSEL0 -- BARH5 BARL5 BDRH5 BDRL5 BARE5 PUCR15 PUCR55 P15 -- P35 P55 P65 P75 P85 P95 PB5 IRQ1 WKP5 -- PCR15 -- PCR35 PCR55 Bit 4 PWDRL4 PWDRU4 -- TCSRWE TCWD4 -- ACMP2 -- BARH4 BARL4 BDRH4 BDRL4 BARE4 PUCR14 PUCR54 P14 P24 P34 P54 P64 P74 P84 P94 PB4 IRQ0 WKP4 POF24 PCR14 PCR24 PCR34 PCR54 Bit 3 PWDRL3 PWDRU3 -- B2WI TCWD3 CKS3 ACMP1 -- BARH3 BARL3 BDRH3 BDRL3 BARE3 -- PUCR53 -- P23 P33 P53 P63 -- P83 P93 PB3 TXD2 WKP3 POF23 -- PCR23 PCR33 PCR53 Bit 2 PWDRL2 PWDRU2 -- WDON TCWD2 CKS2 ACMP0 -- BARH2 BARL2 BDRH2 BDRL2 BARE2 PUCR12 PUCR52 P12 P22 P32 P52 P62 P72 P82 P92 PB2 PWM WKP2 -- PCR12 PCR22 PCR32 PCR52 Bit 1 PWDRL1 PWDRU1 -- B0WI TCWD1 CKS1 DCMP1 -- BARH1 BARL1 BDRH1 BDRL1 BARE1 PUCR11 PUCR51 P11 P21 P31 P51 P61 P71 P81 P91 PB1 TXD WKP1 -- PCR11 PCR21 PCR31 PCR51 Bit 0 PWDRL0 PWDRU0 PWCR0 WRST TCWD0 CKS0 DCMP0 -- BARH0 BARL0 BDRH0 BDRL0 BARE0 PUCR10 PUCR50 P10 P20 P30 P50 P60 P70 P80 P90 PB0 TMOW WKP0 -- PCR10 PCR20 PCR30 PCR50
Module Name 14-bit PWM
WDT*2
Address break
I/O port
Rev. 3.00 Mar. 15, 2006 Page 415 of 526 REJ09B0060-0300
Section 22 List of Registers
Register Name PCR6 PCR7 PCR8 PCR9 SYSCR1 SYSCR2 IEGR1 IEGR2 IENR1 IENR2 IRR1 IRR2 IWPR MSTCR1 MSTCR2 Bit 7 PCR67 PCR77 PCR87 PCR97 SSBY SMSEL NMIEG -- IENDT -- IRRDT -- -- -- MSTS3_2 Bit 6 PCR66 PCR76 PCR86 PCR96 STS2 LSON -- -- IENTA -- IRRTA -- -- MSTIIC -- Bit 5 PCR65 PCR75 PCR85 PCR95 STS1 DTON -- WPEG5 IENWP IENTB1 -- IRRTB1 IWPF5 MSTS3 -- Bit 4 PCR64 PCR74 PCR84 PCR94 STS0 MA2 -- WPEG4 -- -- -- -- IWPF4 MSTAD MSTTB1 Bit 3 PCR63 -- PCR83 PCR93 NESEL MA1 IEG3 WPEG3 IEN3 -- IRRI3 -- IWPF3 MSTWD -- Bit 2 PCR62 PCR72 PCR82 PCR92 -- MA0 IEG2 WPEG2 IEN2 -- IRRI2 -- IWPF2 MSTTW -- Bit 1 PCR61 PCR71 PCR81 PCR91 -- SA1 IEG1 WPEG1 IEN1 -- IRRI1 -- IWPF1 MSTTV MSTTZ Bit 0 PCR60 PCR70 PCR80 PCR90 -- SA0 IEG0 WPEG0 IEN0 -- IRRI0 -- IWPF0 MSTTA MSTPWM
Module Name I/O port
Power-down
Interrupt
Power-down
Notes: 1. LVDC: Low-voltage detection circuits (optional) 2. WDT: Watchdog timer
Rev. 3.00 Mar. 15, 2006 Page 416 of 526 REJ09B0060-0300
Section 22 List of Registers
22.3
Register Name SMR_3 BRR_3 SCR3_3 TDR_3 SSR_3 RDR_3 SMCR_3 TCR_0
Register States in Each Operating Mode
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Active -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Subactive Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Subsleep Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Timer Z1 Timer Z0 Module SCI3_3
TIORA_0 Initialized TIORC_0 Initialized TSR_0 TIER_0 POCR_0 TCNT_0 GRA_0 GRB_0 GRC_0 GRD_0 TCR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
TIORA_1 Initialized TIORC_1 Initialized TSR_1 TIER_1 POCR_1 TCNT_1 GRA_1 GRB_1 GRC_1 GRD_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Rev. 3.00 Mar. 15, 2006 Page 417 of 526 REJ09B0060-0300
Section 22 List of Registers
Register Name TSTR TMDR TPMR TFCR TOER TOCR
Reset Initialized Initialized Initialized Initialized Initialized Initialized
Active -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Subactive -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- --
Subsleep Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Module Timer Z common
RSECDR Initialized RMINDR RHRDR RWKDR RTCCR1 RTCCR2 Initialized Initialized -- -- --
RTC
RTCCSR Initialized LVDCR LVDSR SMR_2 BRR_2 SCR3_2 TDR_2 SSR_2 RDR_2 ICCR1 ICCR2 ICMR ICIER ICSR SAR ICDRT ICDRR TMB1 TCB1 TLB1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
LVDC (optional)*1 SCI3_2
Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
IIC2
Timer B1
Rev. 3.00 Mar. 15, 2006 Page 418 of 526 REJ09B0060-0300
Section 22 List of Registers
Register Name TMRW TCRW TIERW TSRW TIOR0 TIOR1 TCNT GRA GRB GRC GRD FLMCR1 FLMCR2
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Active -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Subactive -- -- -- -- -- -- -- -- -- -- -- Initialized -- -- Initialized -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Subsleep Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Module Timer W
Initialized Initialized -- -- -- --
ROM
FLPWCR Initialized EBR1 FENR TCRV0 TCSRV TCORA TCORB TCNTV TCRV1 SMR BRR SCR3 TDR SSR RDR ADDRA ADDRB ADDRC Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Initialized Initialized -- -- Timer V
Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
SCI3
A/D converter
Rev. 3.00 Mar. 15, 2006 Page 419 of 526 REJ09B0060-0300
Section 22 List of Registers
Register Name ADDRD ADCSR ADCR PWDRL PWDRU PWCR
Reset Initialized Initialized Initialized Initialized Initialized Initialized
Active -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Subactive Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Subsleep Standby Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Module A/D converter
14-bit PWM
TCSRWD Initialized TCWD TMWD Initialized Initialized
WDT*2
ABRKCR Initialized ABRKSR Initialized BARH BARL BDRH BDRL BARE PUCR1 PUCR5 PDR1 PDR2 PDR3 PDR5 PDR6 PDR7 PDR8 PDR9 PDRB PMR1 PMR5 PMR3 PCR1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Address break
I/O port
Rev. 3.00 Mar. 15, 2006 Page 420 of 526 REJ09B0060-0300
Section 22 List of Registers
Register Name PCR2 PCR3 PCR5 PCR6 PCR7 PCR8 PCR9 SYSCR1 SYSCR2 IEGR1 IEGR2 IENR1 IENR2 IRR1 IRR2 IWPR
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Active -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Subactive -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Subsleep Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Module I/O port
Power-down
Interrupt
MSTCR1 Initialized MSTCR2 Initialized
Power-down
Notes: is not initialized 1. LVDC: Low-voltage detection circuits (optional) 2. WDT: Watchdog timer
Rev. 3.00 Mar. 15, 2006 Page 421 of 526 REJ09B0060-0300
Section 22 List of Registers
Rev. 3.00 Mar. 15, 2006 Page 422 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Section 23 Electrical Characteristics
23.1 Absolute Maximum Ratings
Table 23.1 Absolute Maximum Ratings
Item Power supply voltage Analog power supply voltage Input voltage Ports other than ports B and X1 Port B X1 Operating temperature Storage temperature Topr Tstg Symbol VCC AVCC VIN Value -0.3 to +7.0 -0.3 to +7.0 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to 4.3 -20 to +75 -55 to +125 Unit V V V V V C C Notes *
Note: * Permanent damage may result if maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability.
23.2
23.2.1
Electrical Characteristics (F-ZTATTM Version)
Power Supply Voltage and Operating Ranges
Power Supply Voltage and Oscillation Frequency Range
OSC (MHz) 20.0 W (kHz)
32.768 10.0
2.0
3.0 4.0 5.5 * AVCC = 3.0 to 5.5 V * Active mode * Sleep mode
VCC (V)
3.0 4.0 5.5 * AVCC = 3.0 to 5.5 V * All operating modes
VCC (V)
Rev. 3.00 Mar. 15, 2006 Page 423 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Power Supply Voltage and Operating Frequency Range
(MHz) 20.0 SUB (kHz)
16.384 10.0 8.192 1.0 3.0 4.0 5.5 VCC (V) * AVCC = 3.0 to 5.5 V * Active mode * Sleep mode (When MA2 in SYSCR2 = 0 ) 4.096 3.0 4.0 5.5 * AVCC = 3.0 to 5.5 V * Subactive mode * Subsleep mode VCC (V)
(kHz)
2500 1250
78.125 3.0 4.0 5.5 VCC (V) * AVCC = 3.0 to 5.5 V * Active mode * Sleep mode (When MA2 in SYSCR2 = 1 )
Analog Power Supply Voltage and A/D Converter Accuracy Guarantee Range
(MHz)
20.0 10.0
2.0 3.0 4.0 5.5 AVCC (V)
* VCC = 3.0 to 5.5 V * Active mode * Sleep mode
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Section 23 Electrical Characteristics
Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage Detection Circuit is Used
osc (MHz) 20.0 16.0
2.0 Vcc(V) 3.0 4.5 5.5
Operation guarantee range Operation guarantee range except A/D conversion accuracy
Rev. 3.00 Mar. 15, 2006 Page 425 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
23.2.2
DC Characteristics
Table 23.2 DC Characteristics (1) VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Values Item Symbol Applicable Pins RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG,TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, FTIOA to FTIOD, SCK3, SCK3_2, SCK3_3, TRGV, FTCI, TMIB1 RXD, RXD_2, RXD_3, SCL, SDA, P10 to P12, P14 to P17, P20 to P24, P30 to P37, P50 to P57, P60 to P67, P70 to P72, P74 to P77, P80 to P87, P90 to P97 PB0 to PB7 Test Condition Min. Typ. Max. VCC + 0.3 Unit V Notes
Input high VIH voltage
VCC = 4.0 to 5.5 V VCC x 0.8
VCC x 0.9
VCC + 0.3
VCC = 4.0 to 5.5 V VCC x 0.7
VCC + 0.3
V
VCC x 0.8
VCC + 0.3
VCC = 4.0 to 5.5 V VCC x 0.7 VCC x 0.8

AVCC + 0.3 V AVCC + 0.3 VCC + 0.3 VCC + 0.3 V
OSC1
VCC = 4.0 to 5.5 V VCC - 0.5 VCC - 0.3
Note: Connect the TEST pin to Vss.
Rev. 3.00 Mar. 15, 2006 Page 426 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Values Item Input low voltage Symbol VIL Applicable Pins RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG, TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, FTIOA to FTIOD, SCK3, SCK3_2, SCK3_3, TRGV, FTCI, TMIB1 RXD, RXD_2, RXD_3, SCL, SDA, P10 to P12, P14 to P17, P20 to P24, P30 to P37, P50 to P57, P60 to P67, P70 to P72, P74 to P77, P80 to P87, P90 to P97 PB0 to PB7 VCC = 4.0 to 5.5 V VCC = 4.0 to 5.5 V Test Condition VCC = 4.0 to 5.5 V Min. -0.3 Typ. Max. VCC x 0.2 Unit V Notes
-0.3
VCC x 0.1
-0.3
VCC x 0.3
V
-0.3
VCC x 0.2
-0.3 -0.3

VCC x 0.3 VCC x 0.2 0.5 0.3
V
OSC1
VCC = 4.0 to 5.5 V
-0.3 -0.3
V
Rev. 3.00 Mar. 15, 2006 Page 427 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Values Item Output high voltage Symbol VOH Applicable Pins P10 to P12, P14 to P17, P20 to P24, P30 to P37, P50 to P55, P60 to P67, P70 to P72, P74 to P77, P80 to P87, P90 to P97 P56, P57 Test Condition VCC = 4.0 to 5.5 V -IOH = 1.5 mA Min. VCC - 1.0 Typ. Max. Unit V Notes
-IOH = 0.1 mA
VCC - 0.5
4.0 V VCC 5.5 V VCC - 2.5 -IOH = 0.1 mA 3.0 V VCC < 4.0 V VCC - 2.0 -IOH = 0.1 mA

0.6
V
Output low voltage
VOL
P10 to P12, P14 to P17, P20 to P24, P30 to P37, P50 to P57, P70 to P72, P74 to P77, P85 to P87, P90 to P97 P60 to P67, P80 to P84
VCC = 4.0 to 5.5 V IOL = 1.6 mA
V
IOL = 0.4 mA
0.4
VCC = 4.0 to 5.5 V IOL = 20.0 mA VCC = 4.0 to 5.5 V IOL = 10.0 mA VCC = 4.0 to 5.5 V IOL = 1.6 mA IOL = 0.4 mA


1.5 1.0 0.4 0.4 0.6 0.4
V
SCL, SDA
VCC = 4.0 to 5.5 V IOL = 6.0 mA IOL = 3.0 mA
Rev. 3.00 Mar. 15, 2006 Page 428 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Values Item Symbol | IIL | Applicable Pins Test Condition Min. Typ. Max. 1.0 Unit A Notes
OSC1, RES, NMI, VIN = 0.5 V or WKP0 to WKP5, higher (VCC - 0.5 V) IRQ0 to IRQ3, ADTRG, TRGV, TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, FTIOA to FTIOD, RXD, SCK3, RXD_2, SCK3_2, RXD_3, SCK3_3, SCL, SDA, TMIB1, FTCI P10 to P12, P14 to P17, P20 to P24, P30 to P37, P50 to P57, P60 to P67, P70 to P72, P74 to P77, P80 to P87, P90 to P97 PB0 to PB7 VIN = 0.5 V or higher (VCC - 0.5 V)
1.0
A
VIN = 0.5 V or higher (AVCC - 0.5 V) VCC = 5.0 V, VIN = 0.0 V VCC = 3.0 V, VIN = 0.0 V
1.0
A
Pull-up MOS current
-Ip
P10 to P12, P14 to P17, P50 to P55 RES
50.0
60.0 150
300.0
A Reference value k
Pull-up RRES MOS resistance Input capacitance Cin
All input pins except power supply pins
f = 1 MHz, VIN = 0.0 V, Ta = 25C
15.0
pF
Rev. 3.00 Mar. 15, 2006 Page 429 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Values Item Active mode supply current Symbol Applicable Pins IOPE1 VCC Test Condition Active mode 1 VCC = 5.0 V, fOSC = 20 MHz Active mode 1 VCC = 3.0 V, fOSC = 10 MHz IOPE2 VCC Active mode 2 VCC = 5.0 V, fOSC = 20 MHz Active mode 2 VCC = 3.0 V, fOSC = 10 MHz Sleep mode supply current ISLEEP1 VCC Sleep mode 1 VCC = 5.0 V, fOSC = 20 MHz Sleep mode 1 VCC = 3.0 V, fOSC = 10 MHz ISLEEP2 VCC Sleep mode 2 VCC = 5.0 V, fOSC = 20 MHz Sleep mode 2 VCC = 3.0 V, fOSC = 10 MHz Subactive mode supply current ISUB VCC VCC = 3.0 V 32-kHz crystal resonator (SUB = W/2) VCC = 3.0 V 32-kHz crystal resonator (SUB = W/8) Subsleep mode supply current ISUBSP VCC VCC = 3.0 V 32-kHz crystal resonator (SUB = W/2) Min. Typ. 25.0 Max. 36.0 Unit mA Notes *
11.0
* Reference value mA *
2.3
3.6
1.3
* Reference value mA *
18.0
23.0
8.0
* Reference value mA *
2.1
3.1
1.2
* Reference value A *
35.0
70.0
25.0
* Reference value A *
25.0
50.0
Rev. 3.00 Mar. 15, 2006 Page 430 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Values Item Standby mode supply current RAM data retaining voltage Symbol Applicable Pins ISTBY VCC Test Condition 32-kHz crystal resonator not used Min. Typ. Max. 5.0 Unit A Notes *
VRAM
VCC
2.0
V
Note:
*
Pin states during supply current measurement are given below (excluding current in the pull-up MOS transistors and output buffers).
RES Pin VCC Internal State Operates Operates (OSC/64) VCC Only timers operate Only timers operate (OSC/64) VCC VCC VCC Operates Only timers operate CPU and timers both stop VCC VCC VCC Main clock: ceramic or crystal resonator Subclock: crystal resonator Main clock: ceramic or crystal resonator Subclock: Pin X1 = VSS VCC Other Pins VCC Oscillator Pins Main clock: ceramic or crystal resonator Subclock: Pin X1 = VSS
Mode Active mode 1 Active mode 2 Sleep mode 1 Sleep mode 2 Subactive mode Subsleep mode Standby mode
Rev. 3.00 Mar. 15, 2006 Page 431 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Table 23.2 DC Characteristics (2) VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Applicable Item Allowable output low current (per pin) Symbol IOL Pins Output pins except port 6, P80 to P84, SCL, and SDA Port 6, P80 to P84 Output pins except port 6, P80 to P84, SCL, and SDA Port 6, P80 to P84 SCL, SDA Allowable output low current (total) IOL Output pins except port 6, P80 to P84, SCL, and SDA Port 6, P80 to P84, SCL, and SDA Output pins except port 6, P80 to P84, SCL, and SDA Port 6, P80 to P84, SCL, and SDA Allowable output high current (per pin) Allowable output high current (total) -IOH All output pins Test Condition Min. VCC = 4.0 to 5.5 V Values Typ. Max. 2.0 Unit mA


20.0 0.5
VCC = 4.0 to 5.5 V

10.0 6.0 40.0 mA
80.0
20.0
40.0
VCC = 4.0 to 5.5 V

2.0 0.2 30.0 8.0
mA
-IOH
All output pins
VCC = 4.0 to 5.5 V
mA
Rev. 3.00 Mar. 15, 2006 Page 432 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
23.2.3
AC Characteristics
Table 23.3 AC Characteristics VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Applicable Item Symbol Pins OSC1, OSC2 Test Condition VCC = 4.0 to 5.5 V Min. 2.0 2.0 System clock () cycle time tcyc 1 X1, X2 X1, X2 2 2 trc OSC1, OSC2 OSC1, OSC2 X1, X2 OSC1 VCC = 4.0 to 5.5 V Values Typ. Max. 20.0 10.0 64 12.8 tOSC s kHz s tW tcyc tsubcyc ms *
2
Reference Unit MHz Figure *
1
System clock fOSC oscillation frequency
*
2
Subclock oscillation fW frequency Watch clock (W) cycle time Subclock (SUB) cycle time Instruction cycle time Oscillation stabilization time (crystal resonator) tW tsubcyc
32.768 30.5 8 10.0
Oscillation trc stabilization time (ceramic resonator) Oscillation stabilization time External clock high width External clock low width External clock rise time External clock fall time trcx tCPH
5.0
ms
20.0 40.0

2.0 10.0 15.0 10.0 15.0
s ns Figure 23.1
tCPL
OSC1
VCC = 4.0 to 5.5 V
20.0 40.0
ns
tCPr
OSC1
VCC = 4.0 to 5.5 V

ns
tCPf
OSC1
VCC = 4.0 to 5.5 V

ns
Rev. 3.00 Mar. 15, 2006 Page 433 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Applicable Item RES pin low width Symbol tREL Pins RES Test Condition Min.
Values Typ. Max. Unit ms
Reference Figure Figure 23.2
At power-on and in trc modes other than those below In active mode and 200 sleep mode operation
ns
Input pin high width
tIH
NMI, TMBI1, IRQ0 to IRQ3, WKP0 to WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, FTIOA to FTIOD, FTCI NMI, TMBI1, IRQ0 to IRQ3, WKP0 to WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, FTIOA to FTIOD, FTCI
2
tcyc tsubcyc
Figure 23.3
Input pin low width
tIL
2
tcyc tsubcyc
Notes: 1. When an external clock is input, the minimum system clock oscillation frequency is 1.0 MHz. 2. Determined by the MA2, MA1, MA0, SA1, and SA0 bits in the system control register 2 (SYSCR2).
Rev. 3.00 Mar. 15, 2006 Page 434 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Table 23.4 I2C Bus Interface Timing VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Test Condition Values Min. Typ. Max. 300 1tcyc Unit ns ns ns ns ns 12tcyc + 600 3tcyc + 300 5tcyc + 300 Reference Figure Figure 23.4
Item SCL input cycle time SCL input high width SCL input low width SCL and SDA input fall time SCL and SDA input spike pulse removal time SDA input bus-free time Start condition input hold time Retransmission start condition input setup time Setup time for stop condition input Data-input setup time Data-input hold time Capacitive load of SCL and SDA SCL and SDA output fall time
Symbol tSCL tSCLH tSCLL tSf tSP
tBUF tSTAH tSTAS
5tcyc 3tcyc 3tcyc


ns ns ns
tSTOS tSDAS tSDAH cb tSf
3tcyc 1tcyc+20 0 0 VCC = 4.0 to 5.5 V

400 250 300
ns ns ns pF ns
Rev. 3.00 Mar. 15, 2006 Page 435 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Table 23.5 Serial Communication Interface (SCI) Timing VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Applicable Item Symbol Pins SCK3 Test Condition Min. 4 6 Values Typ. Max. Unit tcyc Reference Figure Figure 23.5
Input Asynchro- tScyc clockcycle nous Clocked synchronous Input clock pulse width Transmit data delay time (clocked synchronous) Receive data setup time (clocked synchronous) Receive data hold time (clocked synchronous) tSCKW tTXD
SCK3 TXD VCC = 4.0 to 5.5 V
0.4

0.6 1 1
tScyc tcyc Figure 23.6
tRXS
RXD
VCC = 4.0 to 5.5 V
50.0 100.0
ns
tRXH
RXD
VCC = 4.0 to 5.5 V
50.0 100.0
ns
Rev. 3.00 Mar. 15, 2006 Page 436 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
23.2.4
A/D Converter Characteristics
Table 23.6 A/D Converter Characteristics VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Applicable Pins AVCC AN0 to AN7 AVCC AVCC = 5.0 V fOSC = 20 MHz AVCC 50 A *
2
Item
Symbol
Test Condition
Values Min. 3.0 VSS - 0.3 Typ. Max. VCC 5.5 Unit V Notes *
1
Analog power supply AVCC voltage Analog input voltage AVIN
AVCC + 0.3 V 2.0 mA
Analog power supply AIOPE current AISTOP1
Reference value
AISTOP2 Analog input capacitance Allowable signal source impedance Resolution (data length) Conversion time (single mode) Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Conversion time (single mode) Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy CAIN RAIN
AVCC AN0 to AN7 AN0 to AN7
10 AVCC = 3.0 to 5.5 V 134 AVCC = 4.0 to 5.5 V 70
10
5.0 30.0 5.0 10 7.5 7.5 7.5 0.5 8.0 7.5 7.5 7.5 0.5 8.0
A pF k Bit tcyc LSB LSB LSB LSB LSB tcyc LSB LSB LSB LSB LSB
*
3
Rev. 3.00 Mar. 15, 2006 Page 437 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics Values Min. Typ. Max. 3.5 3.5 3.5 0.5 4.0 Unit tcyc LSB LSB LSB LSB LSB Notes
Item Conversion time (single mode) Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy
Symbol
Applicable Pins
Test Condition
AVCC = 4.0 to 134 5.5 V
Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at reset and in standby, subactive, and subsleep modes while the A/D converter is idle.
23.2.5
Watchdog Timer Characteristics
Table 23.7 Watchdog Timer Characteristics VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Applicable Pins Test Condition Values Min. 0.2 Typ. 0.4 Max. Unit s Notes *
Item Internal oscillator overflow time Note: *
Symbol tOVF
Shows the time to count from 0 to 255, at which point an internal reset is generated, when the internal oscillator is selected.
Rev. 3.00 Mar. 15, 2006 Page 438 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
23.2.6
Flash Memory Characteristics
Table 23.8 Flash Memory Characteristics VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Test Item Programming time (per 128 bytes)* * * Erase time (per block) * * * Reprogramming count Programming Wait time after SWE 1 bit setting* Wait time after PSU 1 bit setting* Wait time after P bit setting* *
14 136 124
Values Min. 1000 1 50 Typ. 7 100 10000 30 200 10 Max. 32 202 12 1000 Unit ms ms Times s s s s s s s s s s s Times
Symbol tP tE NWEC x y z1 z2 z3 Wait time after P bit clear*
1
Condition
1n6 7 n 1000 Additionalprogramming
28 198 8 5 5 4 2 2 100
1
Wait time after PSU bit clear*

Wait time after PV bit setting* Wait time after dummy write* Wait time after PV bit clear*
1
1
1
Wait time after SWE bit clear*
1
Maximum programming 145 count * * *
N
Rev. 3.00 Mar. 15, 2006 Page 439 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Test Item Erasing Wait time after SWE 1 bit setting* Wait time after ESU 1 bit setting* Wait time after E bit setting* * Wait time after E bit clear*
1 16
Values Min. 1 100 10 10 10 20 2 4 100 Typ. Max. 100 120 Unit s s ms s s s s s s Times
Symbol x y z
1
Condition
Wait time after ESU bit clear*

Wait time after EV bit setting* Wait time after dummy write* Wait time after EV bit clear*
1
1
1
Wait time after SWE bit clear*
1
Maximum erase count * * *
167
N
Notes: 1. Make the time settings in accordance with the program/erase algorithms. 2. The programming time for 128 bytes. (Indicates the total time for which the P bit in the flash memory control register 1 (FLMCR1) is set. The program-verify time is not included.) 3. The time required to erase one block. (Indicates the time for which the E bit in the flash memory control register 1 (FLMCR1) is set. The erase-verify time is not included.) 4. Maximum programming time (tP (max.)) = wait time after P bit setting (z) x maximum programming count (N) 5. Set the maximum programming count (N) according to the actual set values of z1, z2, and z3, so that it does not exceed the maximum programming time (tP (max.)). The wait time after P bit setting (z1, z2) should be changed as follows according to the value of the programming count (n). Programming count (n) 1n6 z1 = 30 s 7 n 1000 z2 = 200 s 6. Maximum erase time (tE (max.)) = wait time after E bit setting (z) x maximum erase count (N) 7. Set the maximum erase count (N) according to the actual set value of (z), so that it does not exceed the maximum erase time (tE (max.)).
Rev. 3.00 Mar. 15, 2006 Page 440 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
23.2.7
Power-Supply-Voltage Detection Circuit Characteristics (Optional)
Table 23.9 Power-Supply-Voltage Detection Circuit Characteristics VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Test Condition LVDSEL = 0 LVDSEL = 0 LVDSEL = 0 LVDSEL = 1 LVDE = 1, Vcc = 5.0 V, When a 32kHz crystal resonator is not used Values Min. 3.3 3.0 1.0 50 Typ. 3.7 4.0 2.3 3.6 Max. 4.5 2.7 4.2 350 Unit V V V V V s A
Item
Symbol Vint (D) Vint (U) Vreset1 Vreset2 VLVDRmin tLVDON ISTBY
Power-supply falling detection voltage Power-supply rising detection voltage Reset detection voltage 1*1 Reset detection voltage 2*
2
Lower-limit voltage of LVDR operation*3 LVD stabilization time Supply current in standby mode
Notes: 1. This voltage should be used when the falling and rising voltage detection function is used. 2. Select the low-voltage reset 2 when only the low-voltage detection reset is used. 3. When the power-supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises, a reset may not occur. Therefore sufficient evaluation is required.
Rev. 3.00 Mar. 15, 2006 Page 441 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
23.2.8
Power-On Reset Circuit Characteristics (Optional)
Table 23.10 Power-On Reset Circuit Characteristics VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Test Condition Values Min. 100 Typ. 150 Max. 100 Unit k mV
Item
Symbol RRES Vpor
Pull-up resistance of RES pin Power-on reset start voltage* Note: *
The power-supply voltage (Vcc) must fall below Vpor = 100 mV and then rise after charge of the RES pin is removed completely. In order to remove charge of the RES pin, it is recommended that the diode be placed in the Vcc side. If the power-supply voltage (Vcc) rises from the point over 100 mV, a power-on reset may not occur.
23.3
23.3.1
Electrical Characteristics (Masked ROM Version)
Power Supply Voltage and Operating Ranges
Power Supply Voltage and Oscillation Frequency Range
OSC (MHz) 20.0 W (kHz)
32.768 10.0
2.0
2.7 4.0 5.5 * AVCC = 2.7 to 5.5 V * Active mode * Sleep mode
VCC (V)
2.7 4.0 5.5 * AVCC = 2.7 to 5.5 V * All operating modes
VCC (V)
Rev. 3.00 Mar. 15, 2006 Page 442 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Power Supply Voltage and Operating Frequency Range
(MHz) 20.0 SUB (kHz)
16.384 10.0 8.192 1.0 2.7 4.0 5.5 VCC (V) * AVCC = 2.7 to 5.5 V * Active mode * Sleep mode (When MA2 in SYSCR2 = 0) 4.096 2.7 4.0 5.5 * AVCC = 2.7 to 5.5 V * Subactive mode * Subsleep mode VCC (V)
(kHz)
2500 1250
78.125 2.7 4.0 5.5 VCC (V) * AVCC = 2.7 to 5.5 V * Active mode * Sleep mode (When MA2 in SYSCR2 = 1)
Analog Power Supply Voltage and A/D Converter Accuracy Guarantee Range
(MHz)
20.0 10.0
2.0 3.0 4.0 5.5 AVCC (V)
* VCC = 2.7 to 5.5 V * Active mode * Sleep mode
Rev. 3.00 Mar. 15, 2006 Page 443 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage Detection Circuit is Used
osc (MHz) 20.0 16.0
2.0 Vcc(V) 3.0 4.5 5.5
Operation guarantee range Operation guarantee range except A/D conversion accuracy
Rev. 3.00 Mar. 15, 2006 Page 444 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
23.3.2
DC Characteristics
Table 23.11 DC Characteristics (1) VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Values Item Input high voltage Symbol VIH Applicable Pins RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG,TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, FTIOA to FTIOD, SCK3, SCK3_2, SCK3_3, TRGV, FTCI, TMIB1 RXD, RXD_2, RXD_3, SCL, SDA, P10 to P12, P14 to P17, P20 to P24, P30 to P37 P50 to P57, P60 to P67, P70 to P72, P74 to P77, P80 to P87, P90 to P97 PB0 to PB7 Test Condition Min. Typ. Max. VCC + 0.3 Unit V Notes
VCC = 4.0 to 5.5 V VCC x 0.8
VCC x 0.9
VCC + 0.3
VCC = 4.0 to 5.5 V VCC x 0.7
VCC + 0.3
V
VCC x 0.8
VCC + 0.3
VCC = 4.0 to 5.5 V VCC x 0.7 VCC x 0.8

AVCC + 0.3 V AVCC + 0.3 VCC + 0.3 VCC + 0.3 V
OSC1
VCC = 4.0 to 5.5 V VCC - 0.5 VCC - 0.3
Note: Connect the TEST pin to Vss.
Rev. 3.00 Mar. 15, 2006 Page 445 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Values Item Input low voltage Symbol VIL Applicable Pins RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG,TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, FTIOA to FTIOD, SCK3, SCK3_2, SCK3_3, TRGV, FTCI, TMIB1 RXD, RXD_2, RXD_3, SCL, SDA, P10 to P12, P14 to P17, P20 to P24, P30 to P37, P50 to P57, P60 to P67,. P70 to P72, P74 to P77, P80 to P87, P90 to P97 PB0 to PB7 Test Condition Min. Typ. Max. VCC x 0.2 Unit V Notes
VCC = 4.0 to 5.5 V -0.3
-0.3
VCC x 0.1
VCC = 4.0 to 5.5 V -0.3
VCC x 0.3
V
-0.3
VCC x 0.2
VCC = 4.0 to 5.5 V -0.3 -0.3

VCC x 0.3 VCC x 0.2 0.5 0.3
V
OSC1
VCC = 4.0 to 5.5 V -0.3 -0.3
V
Rev. 3.00 Mar. 15, 2006 Page 446 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Values Item Output high voltage Symbol VOH Applicable Pins P10 to P12, P14 to P17, P20 to P24, P30 to P37, P50 to P55, P60 to P67, P70 to P72, P74 to P76, P80 to P87, P90 to P97 P56, P57 Test Condition VCC = 4.0 to 5.5 V -IOH = 1.5 mA Min. VCC - 1.0 Typ. Max. Unit V Notes
-IOH = 0.1 mA
VCC - 0.5
4.0 V VCC 5.5 V -IOH = 0.1 mA 2.0 V VCC < 4.0 V -IOH = 0.1 mA
VCC - 2.5 VCC - 2.0

0.6
V
Output low voltage
VOL
P10 to P12, P14 to P17, P20 to P24, P30 to P37, P50 to P57, P70 to P72, P74 to P77, P85 to P87, P90 to P97 P60 to P67, P80 to P84
VCC = 4.0 to 5.5 V IOL = 1.6 mA
V
IOL = 0.4 mA
0.4
VCC = 4.0 to 5.5 V IOL = 20.0 mA VCC = 4.0 to 5.5 V IOL = 10.0 mA VCC = 4.0 to 5.5 V IOL = 1.6 mA IOL = 0.4 mA
1.5
V
1.0
0.4


0.4 0.6 V
SCL, SDA
VCC = 4.0 to 5.5 V IOL = 6.0 mA IOL = 3.0 mA
0.4
Rev. 3.00 Mar. 15, 2006 Page 447 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Values Item Input/ output leakage current Symbol | IIL | Applicable Pins Test Condition Min. Typ. Max. 1.0 Unit A Notes
OSC1, RES, NMI, VIN = 0.5 V or WKP0 to WKP5, higher (VCC - 0.5 V) IRQ0 to IRQ3, ADTRG, TRGV, TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, FTIOA to FTIOD, RXD, SCK3, RXD_2, SCK3_2, RXD_3, SCK3_3, SCL, SDA, TMIB1, FTCI P10 to P12, P14 to P17, P20 to P24, P30 to P37, P50 to P57, P60 to P67, P70 to P72, P74 to P77, P80 to P87, P90 to P97 PB0 to PB7 VIN = 0.5 V or higher (VCC - 0.5 V)
1.0
A
VIN = 0.5 V or higher (AVCC - 0.5 V) VCC = 5.0 V, VIN = 0.0 V VCC = 3.0 V, VIN = 0.0 V
1.0
A
Pull-up MOS current
-Ip
P10 to P12, P14 to P17, P50 to P55
50.0
300.0
A

60.0 150
k
Reference value
RRES Pull-up MOS resistance Input capacitance Cin
RES
All input pins except power supply pins
f = 1 MHz, VIN = 0.0 V, Ta = 25C
15.0
pF
Rev. 3.00 Mar. 15, 2006 Page 448 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Values Item Active mode supply current Symbol IOPE1 Applicable Pins VCC Test Condition Active mode 1 VCC = 5.0 V, fOSC = 20 MHz Active mode 1 VCC = 3.0 V, fOSC = 10 MHz IOPE2 VCC Active mode 2 VCC = 5.0 V, fOSC = 20 MHz Active mode 2 VCC = 3.0 V, fOSC = 10 MHz Sleep mode supply current ISLEEP1 VCC Sleep mode 1 VCC = 5.0 V, fOSC = 20 MHz Sleep mode 1 VCC = 3.0 V, fOSC = 10 MHz ISLEEP2 VCC Sleep mode 2 VCC = 5.0 V, fOSC = 20 MHz Sleep mode 2 VCC = 3.0 V, fOSC = 10 MHz Subactive mode supply current ISUB VCC VCC = 3.0 V 32-kHz crystal resonator (SUB = W/2) VCC = 3.0 V 32-kHz crystal resonator (SUB = W/8) Subsleep mode supply current ISUBSP VCC VCC = 3.0 V 32-kHz crystal resonator (SUB = W/2) Min. Typ. 25.0 Max. 36.0 Unit mA Notes *
11.0
* Reference value mA *
2.3
3.6
1.3
* Reference value mA *
18.0
23.0
8.0
* Reference value mA *
2.1
3.1
1.2
* Reference value A *
35.0
70.0
25.0
* Reference value A *
25.0
50.0
Rev. 3.00 Mar. 15, 2006 Page 449 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Values Item Standby mode supply current RAM data retaining voltage Symbol ISTBY Applicable Pins Test Condition VCC Min. Typ. Max. 5.0 Unit A Notes
32-kHz crystal resonator not used
VRAM
VCC
2.0
V
Note:
*
Pin states during supply current measurement are given below (excluding current in the pull-up MOS transistors and output buffers).
RES Pin VCC Internal State Operates Other Pins VCC Oscillator Pins Main clock: ceramic or crystal resonator Subclock: Pin X1 = VSS VCC
Mode Active mode 1
Active mode 2 Sleep mode 1 Sleep mode 2 Subactive mode VCC VCC
Operates (OSC/64) Only timers operate Only timers operate (OSC/64) Operates VCC
Main clock: ceramic or crystal resonator Subclock: crystal resonator Main clock: ceramic or crystal resonator Subclock: Pin X1 = VSS
Subsleep mode Standby mode
VCC VCC
Only timers operate CPU and timers both stop
VCC VCC
Rev. 3.00 Mar. 15, 2006 Page 450 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Table 23.11 DC Characteristics (2) VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Applicable Item Allowable output low current (per pin) Symbol IOL Pins Output pins except port 6, P80 to P84, SCL, and SDA Port 6, P80 to P84 Output pins except port 6, P80 to P84, SCL, and SDA Port 6, P80 to P84 SCL, SDA Allowable output low current (total) IOL Output pins except port 6, P80 to P84, SCL, and SDA Port 6, P80 to P84, SCL, and SDA Output pins except port 6, P80 to P84, SCL, and SDA Port 6, P80 to P84, SCL, and SDA Allowable output high -IOH current (per pin) Allowable output high -IOH current (total) All output pins VCC = 4.0 to 5.5 V VCC = 4.0 to 5.5 V Test Condition VCC = 4.0 to 5.5 V Min. Values Typ. Max. 2.0 Unit mA


20.0 0.5


10.0 6.0 40.0 mA
80.0
20.0
40.0


2.0 0.2 30.0 8.0
mA
All output pins
VCC = 4.0 to 5.5 V

mA
Rev. 3.00 Mar. 15, 2006 Page 451 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
23.3.3
AC Characteristics
Table 23.12 AC Characteristics VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Applicable Item System clock oscillation frequency System clock () cycle time Subclock oscillation frequency Watch clock (W) cycle time Subclock (SUB) cycle time Instruction cycle time Oscillation stabilization time (crystal resonator) trc OSC1, OSC2 OSC1, OSC2 X1, X2 OSC1 VCC = 4.0 to 5.5 V Symbol fOSC Pins OSC1, OSC2 Test Condition VCC = 4.0 to 5.5 V Min. 2.0 2.0 tcyc 1 fW X1, X2 Values Typ. Max. 20.0 10.0 64 12.8 tOSC s kHz *
2
Reference Unit MHz Figure *
1
32.768
tW tsubcyc
X1, X2
2 2
30.5
8 10.0
s tW tcyc tsubcyc ms *
2
trc Oscillation stabilization time (ceramic resonator) Oscillation stabilization time External clock high width External clock low width External clock rise time External clock fall time trcx tCPH
5.0
ms
2.0 10.0 15.0 10.0 15.0
s ns Figure 23.1
205.0 40.0
tCPL
OSC1
VCC = 4.0 to 5.5 V
20.0 40.0
ns
tCPr
OSC1
VCC = 4.0 to 5.5 V

ns
tCPf
OSC1
VCC = 4.0 to 5.5 V

ns
Rev. 3.00 Mar. 15, 2006 Page 452 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Applicable Item RES pin low width Symbol tREL Pins RES Test Condition Min.
Values Typ. Max. Unit ms
Reference Figure Figure 23.2
At power-on and in trc modes other than those below In active mode and sleep mode operation 200
ns
Input pin high width
tIH
NMI, TMBI1, IRQ0 to IRQ3, WKP0 to WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, FTIOA to FTIOD, FTCI NMI, TMBI1, IRQ0 to IRQ3, WKP0 to WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, FTIOA to FTIOD, FTCI
2
tcyc tsubcyc
Figure 23.3
Input pin low width
tIL
2
tcyc tsubcyc
Notes: 1. When an external clock is input, the minimum system clock oscillation frequency is 1.0 MHz. 2. Determined by the MA2, MA1, MA0, SA1, and SA0 bits in the system control register 2 (SYSCR2).
Rev. 3.00 Mar. 15, 2006 Page 453 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Table 23.13 I2C Bus Interface Timing VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Test Condition Min. Values Typ. Max. 300 1tcyc Unit ns ns ns ns ns Reference Figure Figure 23.4
Item SCL input cycle time SCL input high width SCL input low width SCL and SDA input fall time SCL and SDA input spike pulse removal time SDA input bus-free time Start condition input hold time Retransmission start condition input setup time Setup time for stop condition input
Symbol tSCL tSCLH tSCLL tSf tSP
12tcyc + 600 3tcyc + 300 5tcyc + 300
tBUF tSTAH tSTAS
5tcyc 3tcyc 3tcyc


ns ns ns
tSTOS
3tcyc 1tcyc+20 0 0 VCC = 4.0 to 5.5 V

400 250 300
ns ns ns pF ns
Data-input setup time tSDAS Data-input hold time Capacitive load of SCL and SDA SCL and SDA output fall time tSDAH cb tSf
Rev. 3.00 Mar. 15, 2006 Page 454 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Table 23.14 Serial Communication Interface (SCI) Timing VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Applicable Item Input clock cycle Asynchronous Clocked synchronous tSCKW tTXD SCK3 TXD VCC = 4.0 to 5.5 V Symbol tScyc Pins SCK3 Test Condition Min. 4 6 0.4 tRXS RXD VCC = 4.0 to 5.5 V 50.0 100.0 tRXH RXD VCC = 4.0 to 5.5 V 50.0 100.0 Values Typ. Max. Unit 0.6 1 1 ns ns tScyc tcyc Figure 23.6 tcyc Reference Figure Figure 23.5
Input clock pulse width Transmit data delay time (clocked synchronous) Receive data setup time (clocked synchronous) Receive data hold time (clocked synchronous)
Rev. 3.00 Mar. 15, 2006 Page 455 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
23.3.4
A/D Converter Characteristics
Table 23.15 A/D Converter Characteristics VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Applicable Test Symbol Pins Condition AVCC AVIN AIOPE AVCC AN0 to AN7 AVCC AVCC = 5.0 V fOSC = 20 MHz AISTOP1 AVCC 50 A * Reference value *
3 2
Values Min. 2.7 VSS - 0.3 Typ. VCC Max. 5.5 Unit V Notes *
1
Item Analog power supply voltage Analog input voltage Analog power supply current
AVCC + 0.3 V 2.0 mA
AISTOP2 Analog input capacitance CAIN
AVCC AN0 to AN7 AN0 to AN7
10 AVCC = 2.7 to 5.5 V 134 AVCC = 4.0 to 5.5 V 70
10
5.0 30.0 5.0 10 7.5 7.5 7.5 0.5 8.0 7.5 7.5 7.5 0.5 8.0
A pF k Bit tcyc LSB LSB LSB LSB LSB tcyc LSB LSB LSB LSB LSB
Allowable signal source RAIN impedance Resolution (data length) Conversion time (single mode) Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Conversion time (single mode) Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy
Rev. 3.00 Mar. 15, 2006 Page 456 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics Values Min. Typ. Max. 3.5 3.5 3.5 0.5 4.0 Unit tcyc LSB LSB LSB LSB LSB Notes
Item Conversion time (single mode) Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy
Applicable Test Symbol Pins Condition
AVCC = 4.0 to 5.5 134 V
Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at reset and in standby, subactive, and subsleep modes while the A/D converter is idle.
23.3.5
Watchdog Timer Characteristics
Table 23.16 Watchdog Timer Characteristics VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Applicable Item Internal oscillator overflow time Note: * Symbol tOVF Pins Test Condition Min. 0.2 Values Typ. 0.4 Max. Unit s Notes *
Shows the time to count from 0 to 255, at which point an internal reset is generated, when the internal oscillator is selected.
Rev. 3.00 Mar. 15, 2006 Page 457 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
23.3.6
Power-Supply-Voltage Detection Circuit Characteristics (Optional)
Table 23.17 Power-Supply-Voltage Detection Circuit Characteristics VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Test Condition LVDSEL = 0 LVDSEL = 0 LVDSEL = 0 LVDSEL = 1 LVDE = 1, Vcc = 5.0 V, When a 32kHz crystal resonator is not used Values Min. 3.3 3.0 1.0 50 Typ. 3.7 4.0 2.3 3.6 Max. 4.5 2.7 4.2 350 Unit V V V V V s A
Item
Symbol Vint (D) Vint (U) Vreset1 Vreset2 VLVDRmin tLVDON ISTBY
Power-supply falling detection voltage Power-supply rising detection voltage Reset detection voltage 1*1 Reset detection voltage 2*
2
Lower-limit voltage of LVDR operation*3 LVD stabilization time Supply current in standby mode
Notes: 1. This voltage should be used when the falling and rising voltage detection function is used. 2. Select the low-voltage reset 2 when only the low-voltage detection reset is used. 3. When the power-supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises, a reset may not occur. Therefore sufficient evaluation is required.
Rev. 3.00 Mar. 15, 2006 Page 458 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
23.3.7
Power-On Reset Circuit Characteristics (Optional)
Table 23.18 Power-On Reset Circuit Characteristics VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Test Condition Values Min. 100 Typ. 150 Max. 100 Unit k mV
Item
Symbol RRES Vpor
Pull-up resistance of RES pin Power-on reset start voltage* Note: *
The power-supply voltage (Vcc) must fall below Vpor = 100 mV and then rise after charge of the RES pin is removed completely. In order to remove charge of the RES pin, it is recommended that the diode be placed in the Vcc side. If the power-supply voltage (Vcc) rises from the point over 100 mV, a power-on reset may not occur.
23.4
Operation Timing
t OSC
OSC1
VIH VIL t CPH t CPr t CPL t CPf
Figure 23.1 System Clock Input Timing
VCC
VCC x 0.7
OSC1 tREL RES VIL tREL
VIL
Figure 23.2 RES Low Width Timing
Rev. 3.00 Mar. 15, 2006 Page 459 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
NMI, IRQ0 to IRQ3, WKP0 to WKP5, ADTRG, FTIOA to FTIOD, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, TMCIV, TMRIV, TRGV, FTCI, TMIB1
VIH VIL t IL t IH
Figure 23.3 Input Timing
SDA tBUF
VIH VIL tSTAH tSCLH tSTAS tSP tSTOS
SCL P* S* tSf tSCLL tSCL tSDAH Sr* tSDAS P*
Note: * S, P, and Sr represent the following: S: Start condition P: Stop condition Sr: Retransmission start condition
Figure 23.4 I2C Bus Interface Input/Output Timing
tSCKW
SCK3
tScyc
Figure 23.5 SCK3 Input Clock Timing
Rev. 3.00 Mar. 15, 2006 Page 460 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
t Scyc
SCK3
VIH or V * OH VIL or V OL * t TXD
TXD (transmit data)
VOH * VOL * t RXS t RXH
RXD (receive data)
Note:
* Output timing reference levels Output high: V OH = 2.0 V Output low: V OL = 0.8 V Load conditions are shown in figure 23.7.
Figure 23.6 SCI Input/Output Timing in Clocked Synchronous Mode
23.5
Output Load Condition
VCC
2.4 k
LSI output pin 30 pF 12 k
Figure 23.7 Output Load Circuit
Rev. 3.00 Mar. 15, 2006 Page 461 of 526 REJ09B0060-0300
Section 23 Electrical Characteristics
Rev. 3.00 Mar. 15, 2006 Page 462 of 526 REJ09B0060-0300
Appendix
Appendix
A.
A.1
Instruction Set
Instruction List
Condition Code
Symbol Rd Rs Rn ERd ERs ERn (EAd) (EAs) PC SP CCR N Z V C disp + - x / Description General destination register General source register General register General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) Destination operand Source operand Program counter Stack pointer Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Displacement Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right Addition of the operands on both sides Subtraction of the operand on the right from the operand on the left Multiplication of the operands on both sides Division of the operand on the left by the operand on the right Logical AND of the operands on both sides Logical OR of the operands on both sides
Rev. 3.00 Mar. 15, 2006 Page 463 of 526 REJ09B0060-0300
Appendix
Symbol ( ), < >
Description Logical exclusive OR of the operands on both sides NOT (logical complement) Contents of operand
Condition Code Notation (cont)
Symbol
Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1 Not affected by execution of the instruction Varies depending on conditions, described in notes
* 0 1 --
Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers (R0 to R7 and E0 to E7).
Rev. 3.00 Mar. 15, 2006 Page 464 of 526 REJ09B0060-0300
Appendix
Table A.1
Instruction Set
1. Data Transfer Instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+
No. of States*1
Mnemonic
Operand Size
Condition Code Operation
Advanced @(d, PC) Normal @@aa
@(d, ERn)
@ERn
@aa
#xx
Rn
--
I #xx:8 Rd8
H
N
Z
V 0 0 0 0 0 0
C -- -- -- -- -- --
MOV
MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd
B B B B B B
2 2 2 4 8 2
---- ---- ---- ---- ---- ----
2 2 4 6 10 6
Rs8 Rd8 @ERs Rd8 @(d:16, ERs) Rd8 @(d:24, ERs) Rd8 @ERs Rd8 ERs32+1 ERs32 @aa:8 Rd8 @aa:16 Rd8 @aa:24 Rd8 Rs8 @ERd 4 8 2 Rs8 @(d:16, ERd) Rs8 @(d:24, ERd) ERd32-1 ERd32 Rs8 @ERd Rs8 @aa:8 Rs8 @aa:16 Rs8 @aa:24 #xx:16 Rd16 Rs16 Rd16 2 4 8 2 @ERs Rd16 @(d:16, ERs) Rd16 @(d:24, ERs) Rd16 @ERs Rd16 ERs32+2 @ERd32 @aa:16 Rd16 @aa:24 Rd16 Rs16 @ERd 4 8 Rs16 @(d:16, ERd) Rs16 @(d:24, ERd)
MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @ERd MOV.B Rs, @(d:16, ERd) MOV.B Rs, @(d:24, ERd) MOV.B Rs, @-ERd
B B B B B B B 2
2 4 6
---- ---- ---- ---- ---- ---- ----
0 0 0 0 0 0 0
-- -- -- -- -- -- --
4 6 8 4 6 10 6
MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd MOV.W @(d:16, ERs), Rd MOV.W @(d:24, ERs), Rd MOV.W @ERs+, Rd
B B B W W W W W W 4 2
2 4 6
---- ---- ---- ---- ---- ---- ---- ---- ----
0 0 0 0 0 0 0 0 0
-- -- -- -- -- -- -- -- --
4 6 8 4 2 4 6 10 6
MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd MOV.W Rs, @(d:16, ERd) MOV.W Rs, @(d:24, ERd)
W W W W W 2
4 6
---- ---- ---- ---- ----
0 0 0 0 0
-- -- -- -- --
6 8 4 6 10
Rev. 3.00 Mar. 15, 2006 Page 465 of 526 REJ09B0060-0300
Appendix
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+
No. of States*1
Mnemonic
Operand Size
Condition Code Operation
Advanced @(d, PC) Normal @@aa
@(d, ERn)
@ERn
@aa
#xx
Rn
--
I ERd32-2 ERd32 Rs16 @ERd Rs16 @aa:16 Rs16 @aa:24 #xx:32 ERd32 ERs32 ERd32
H
N
Z
V 0
C --
MOV
MOV.W Rs, @-ERd
W
2
----
6
MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 MOV.L #xx:32, ERd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16, ERs), ERd MOV.L @(d:24, ERs), ERd MOV.L @ERs+, ERd
W W L L L L L L 6 2 4 6 10 4
4 6
---- ---- ---- ---- ---- ---- ---- ----
0 0 0 0 0 0 0 0
-- -- -- -- -- -- -- --
6 8 6 2 8 10 14 10
@ERs ERd32 @(d:16, ERs) ERd32 @(d:24, ERs) ERd32 @ERs ERd32 ERs32+4 ERs32 @aa:16 ERd32 @aa:24 ERd32 ERs32 @ERd 6 10 4 ERs32 @(d:16, ERd) ERs32 @(d:24, ERd) ERd32-4 ERd32 ERs32 @ERd ERs32 @aa:16 ERs32 @aa:24 2 @SP Rn16 SP+2 SP 4 @SP ERn32 SP+4 SP 2 SP-2 SP Rn16 @SP 4 SP-4 SP ERn32 @SP
MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs, @ERd MOV.L ERs, @(d:16, ERd) MOV.L ERs, @(d:24, ERd) MOV.L ERs, @-ERd
L L L L L L 4
6 8
---- ---- ---- ---- ---- ----
0 0 0 0 0 0
-- -- -- -- -- --
10 12 8 10 14 10
MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 POP POP.W Rn
L L W
6 8
---- ---- ----
0 0 0
-- -- --
10 12 6
POP.L ERn
L
----
0
--
10
PUSH PUSH.W Rn
W
----
0
--
6
PUSH.L ERn
L
----
0
--
10
MOVFPE @aa:16, Rd MOVFPE
B
4
Cannot be used in this LSI
Cannot be used in this LSI Cannot be used in this LSI
MOVTPE Rs, @aa:16 MOVTPE
B
4
Cannot be used in this LSI
Rev. 3.00 Mar. 15, 2006 Page 466 of 526 REJ09B0060-0300
Appendix
2. Arithmetic Instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
@-ERn/@ERn+
Mnemonic
Operand Size
Condition Code Operation
@(d, ERn)
I Rd8+#xx:8 Rd8 -- --
H
N
Z
V
C
ADD
ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd
B B W W L
2 2 4 2 6
2 2 4 2 6
Rd8+Rs8 Rd8 Rd16+#xx:16 Rd16 Rd16+Rs16 Rd16 ERd32+#xx:32 ERd32 ERd32+ERs32 ERd32 Rd8+#xx:8 +C Rd8
-- (1) -- (1) -- (2)
ADD.L ERs, ERd
L
2
-- (2)
2
ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd ADDS ADDS.L #1, ERd ADDS.L #2, ERd ADDS.L #4, ERd INC INC.B Rd INC.W #1, Rd INC.W #2, Rd INC.L #1, ERd INC.L #2, ERd DAA DAA Rd
B B L L L B W W L L B
2 2 2 2 2 2 2 2 2 2 2
-- --
(3) (3)
2 2 2 2 2 2 2 2 2 2 2
Rd8+Rs8 +C Rd8 ERd32+1 ERd32 ERd32+2 ERd32 ERd32+4 ERd32 Rd8+1 Rd8 Rd16+1 Rd16 Rd16+2 Rd16 ERd32+1 ERd32 ERd32+2 ERd32 Rd8 decimal adjust Rd8
------------ ------------ ------------
---- ---- ---- ---- ---- -- *
-- -- -- -- --
*
SUB
SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd SUB.L ERs, ERd
B W W L L B B L L L B W W 2 6 4
2
--
Rd8-Rs8 Rd8 Rd16-#xx:16 Rd16 Rd16-Rs16 Rd16 ERd32-#xx:32 ERd32 ERd32-ERs32 ERd32 Rd8-#xx:8-C Rd8 Rd8-Rs8-C Rd8 ERd32-1 ERd32 ERd32-2 ERd32 ERd32-4 ERd32 Rd8-1 Rd8 Rd16-1 Rd16 Rd16-2 Rd16
2 4 2 6 2 2 2 2 2 2 2 2 2
-- (1) -- (1) -- (2) -- (2)
2
2
SUBX SUBX.B #xx:8, Rd SUBX.B Rs, Rd SUBS SUBS.L #1, ERd SUBS.L #2, ERd SUBS.L #4, ERd DEC DEC.B Rd DEC.W #1, Rd DEC.W #2, Rd
-- --
(3) (3)
2 2 2 2 2 2 2
------------ ------------ ------------
---- ---- ----
-- -- --
Rev. 3.00 Mar. 15, 2006 Page 467 of 526 REJ09B0060-0300
Advanced
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
Appendix
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+
No. of States*1
Mnemonic
Operand Size
Condition Code Operation
Advanced @(d, PC) Normal @@aa
@(d, ERn)
@ERn
@aa
#xx
Rn
--
I ERd32-1 ERd32 ERd32-2 ERd32 Rd8 decimal adjust Rd8
H
N
Z
V
C -- -- --
DEC
DEC.L #1, ERd DEC.L #2, ERd
L L B
2 2 2
---- ---- -- *
2 2 2
DAS
DAS.Rd
*
MULXU MULXU. B Rs, Rd
B
2
Rd8 x Rs8 Rd16 (unsigned multiplication) Rd16 x Rs16 ERd32 (unsigned multiplication) Rd8 x Rs8 Rd16 (signed multiplication) Rd16 x Rs16 ERd32 (signed multiplication) Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (unsigned division)
------------
14
MULXU. W Rs, ERd
W
2
------------
22
MULXS MULXS. B Rs, Rd
B
4
----
----
16
MULXS. W Rs, ERd
W
4
----
----
24
DIVXU DIVXU. B Rs, Rd
B
2
-- -- (6) (7) -- --
14
DIVXU. W Rs, ERd
W
2
ERd32 / Rs16 ERd32 (Ed: remainder, Rd: quotient) (unsigned division)
-- -- (6) (7) -- --
22
DIVXS DIVXS. B Rs, Rd
B
4
Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (signed division)
-- -- (8) (7) -- --
16
DIVXS. W Rs, ERd
W
4
ERd32 / Rs16 ERd32 (Ed: remainder, Rd: quotient) (signed division)
-- -- (8) (7) -- --
24

CMP
CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd
B B W W L L
2 2 4 2 6 2
Rd8-#xx:8 Rd8-Rs8 Rd16-#xx:16 Rd16-Rs16 ERd32-#xx:32 ERd32-ERs32
-- --
2 2 4 2 4 2
-- (1) -- (1) -- (2) -- (2)
Rev. 3.00 Mar. 15, 2006 Page 468 of 526 REJ09B0060-0300
Appendix
Addressing Mode and Instruction Length (bytes)
No. of States*1
@-ERn/@ERn+
Mnemonic
Operand Size
Condition Code Operation
@(d, ERn)
I 0-Rd8 Rd8 0-Rd16 Rd16 0-ERd32 ERd32 0 ( of Rd16) 0 ( of ERd32) ( of Rd16) ( of Rd16) ( of ERd32) ( of ERd32) -- -- --
H
N
Z
V
C

NEG
NEG.B Rd NEG.W Rd NEG.L ERd
B W L W
2 2 2 2
2 2 2 2
EXTU
EXTU.W Rd
----
0
0
--
EXTU.L ERd
L
2
----
0
0
--
2
EXTS
EXTS.W Rd
W
2
----
0
--
2
EXTS.L ERd
L
2
----
0
--
2
Rev. 3.00 Mar. 15, 2006 Page 469 of 526 REJ09B0060-0300
Advanced
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
Appendix
3. Logic Instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+
No. of States*1
Mnemonic
Operand Size
Condition Code Operation
Advanced @(d, PC) Normal @@aa
@(d, ERn)
@ERn
@aa
#xx
Rn
--
I Rd8#xx:8 Rd8
H
N
Z
V 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
C -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
AND
AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd
B B W W L L B B W W L L B B W W L L B W L
2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2
---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2
Rd8Rs8 Rd8 Rd16#xx:16 Rd16 Rd16Rs16 Rd16 ERd32#xx:32 ERd32 ERd32ERs32 ERd32 Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 Rd16Rs16 Rd16 ERd32#xx:32 ERd32 ERd32ERs32 ERd32 Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 Rd16Rs16 Rd16 ERd32#xx:32 ERd32 ERd32ERs32 ERd32 ~ Rd8 Rd8 ~ Rd16 Rd16 ~ Rd32 Rd32
OR
OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd
XOR
XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd
NOT
NOT.B Rd NOT.W Rd NOT.L ERd
Rev. 3.00 Mar. 15, 2006 Page 470 of 526 REJ09B0060-0300
Appendix
4. Shift Instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+
No. of States*1
Mnemonic
Operand Size
Condition Code Operation
Advanced @(d, PC) Normal @@aa
@(d, ERn)
@ERn
@aa
#xx
Rn
--
I C MSB LSB C MSB C MSB 0 MSB C MSB LSB C MSB C MSB LSB C MSB LSB LSB LSB LSB C LSB 0 0
H
N
Z
V
C
SHAL SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR SHLR.B Rd SHLR.W Rd SHLR.L ERd ROTXL ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd ROTL ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR ROTR.B Rd ROTR.W Rd ROTR.L ERd
B W L B W L B W L B W L B W L B W L B W L B W L
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rev. 3.00 Mar. 15, 2006 Page 471 of 526 REJ09B0060-0300
Appendix
5. Bit-Manipulation Instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+
No. of States*1
Mnemonic
Operand Size
Condition Code Operation
Advanced @(d, PC) Normal @@aa
@(d, ERn)
@ERn
@aa
#xx
Rn
--
I (#xx:3 of Rd8) 1
H
N
Z
V
C
BSET BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BCLR BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 BNOT BNOT #xx:3, Rd
B B B B B B B B B B B B B
2 4 4 2 4 4 2 4 4 2 4 4 2
------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------
2 8 8 2 8 8 2 8 8 2 8 8 2
(#xx:3 of @ERd) 1 (#xx:3 of @aa:8) 1 (Rn8 of Rd8) 1 (Rn8 of @ERd) 1 (Rn8 of @aa:8) 1 (#xx:3 of Rd8) 0 (#xx:3 of @ERd) 0 (#xx:3 of @aa:8) 0 (Rn8 of Rd8) 0 (Rn8 of @ERd) 0 (Rn8 of @aa:8) 0 (#xx:3 of Rd8) ~ (#xx:3 of Rd8) (#xx:3 of @ERd) ~ (#xx:3 of @ERd) (#xx:3 of @aa:8) ~ (#xx:3 of @aa:8) (Rn8 of Rd8) ~ (Rn8 of Rd8) (Rn8 of @ERd) ~ (Rn8 of @ERd) (Rn8 of @aa:8) ~ (Rn8 of @aa:8) ~ (#xx:3 of Rd8) Z
BNOT #xx:3, @ERd
B
4
------------
8
BNOT #xx:3, @aa:8
B
4
------------
8
BNOT Rn, Rd
B
2
------------
2
BNOT Rn, @ERd
B
4
------------
8
BNOT Rn, @aa:8
B
4
------------
8
BTST
BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8
B B B B B B B
2 4 4 2 4 4 2
------ ------ ------ ------ ------ ------
---- ---- ---- ---- ---- ----
2 6 6 2 6 6 2
~ (#xx:3 of @ERd) Z ~ (#xx:3 of @aa:8) Z ~ (Rn8 of @Rd8) Z ~ (Rn8 of @ERd) Z ~ (Rn8 of @aa:8) Z (#xx:3 of Rd8) C
BLD
BLD #xx:3, Rd
----------
Rev. 3.00 Mar. 15, 2006 Page 472 of 526 REJ09B0060-0300
Appendix
Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+
No. of States*1
Mnemonic
Operand Size
Condition Code Operation Advanced 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 @(d, PC) Normal @@aa
@(d, ERn)
@ERn
@aa
#xx
Rn
--
I (#xx:3 of @ERd) C
H
N
Z
V
C
BLD
BLD #xx:3, @ERd BLD #xx:3, @aa:8
B B B B B B B B B B B B B B B B B B B B B B B B B B B B B 2 2 2 2 2 2 2 2 2
4 4
---------- ---------- ---------- ---------- ----------
(#xx:3 of @aa:8) C ~(#xx:3 of Rd8) C ~ (#xx:3 of @ERd) C
BILD
BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8
4 4
~(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C (#xx:3 of @ERd24)
BST
BST #xx:3, Rd BST #xx:3, @ERd BST #xx:3, @aa:8
------------ ------------ ------------ ------------ ------------ ------------ ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ----------
4 4
C (#xx:3 of @aa:8) ~ C (#xx:3 of Rd8) ~ C (#xx:3 of @ERd24)
BIST
BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8
4 4
~ C (#xx:3 of @aa:8) C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C
BAND BAND #xx:3, Rd BAND #xx:3, @ERd BAND #xx:3, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @ERd BIAND #xx:3, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BIOR BIOR #xx:3, Rd BIOR #xx:3, @ERd BIOR #xx:3, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8
4 4
C(#xx:3 of @aa:8) C C ~ (#xx:3 of Rd8) C C~ (#xx:3 of @ERd24) C
4 4
C ~ (#xx:3 of @aa:8) C C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C
4 4
C(#xx:3 of @aa:8) C C ~ (#xx:3 of Rd8) C C ~ (#xx:3 of @ERd24) C
4 4
C ~ (#xx:3 of @aa:8) C C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C
4 4
C(#xx:3 of @aa:8) C C ~(#xx:3 of Rd8) C C ~(#xx:3 of @ERd24) C
4 4
C ~ (#xx:3 of @aa:8) C
Rev. 3.00 Mar. 15, 2006 Page 473 of 526 REJ09B0060-0300
Appendix
6. Branching Instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+
No. of States*1
Mnemonic
Operand Size
Condition Code Operation
Advanced @(d, PC) Normal @@aa
@(d, ERn)
@ERn
@aa
Branch Condition If condition is true then PC PC+d else next; C Z = 0 Never Always
#xx
Rn
--
I
H
N
Z
V
C
Bcc
BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4
------------ ------------ ------------ ------------ ------------ ------------
4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6
C Z = 1
------------ ------------
C=0
------------ ------------
C=1
------------ ------------
Z=0
------------ ------------
Z=1
------------ ------------
V=0
------------ ------------
V=1
------------ ------------
N=0
------------ ------------
N=1
------------ ------------
NV = 0
------------ ------------
NV = 1
------------ ------------
Z (NV) = 0
------------ ------------
Z (NV) = 1
------------ ------------
Rev. 3.00 Mar. 15, 2006 Page 474 of 526 REJ09B0060-0300
Appendix
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+
No. of States*1
Operand Size
Condition Code Operation
Advanced @(d, PC) Normal @@aa
Mnemonic
@(d, ERn)
@ERn
@aa
#xx
Rn
--
I PC ERn
H
N
Z
V
C
JMP
JMP @ERn JMP @aa:24 JMP @@aa:8
-- -- -- --
2 4 2 2
------------ ------------ ------------ ------------ 8 6
4 6 10 8
PC aa:24 PC @aa:8 PC @-SP PC PC+d:8 PC @-SP PC PC+d:16 PC @-SP PC ERn PC @-SP PC aa:24 PC @-SP PC @aa:8 2 PC @SP+
BSR
BSR d:8
BSR d:16
--
4
------------
8
10
JSR
JSR @ERn
--
2
------------
6
8
JSR @aa:24
--
4
------------
8
10
JSR @@aa:8
--
2
------------
8
12
RTS
RTS
--
------------
8
10
Rev. 3.00 Mar. 15, 2006 Page 475 of 526 REJ09B0060-0300
Appendix
7. System Control Instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+
No. of States*1
Mnemonic
Operand Size
Condition Code Operation
Advanced @(d, PC) Normal @@aa
@(d, ERn)
@ERn
@aa
#xx
Rn
--
I 1
H
N
Z
V
C
TRAPA TRAPA #x:2
--
2 PC @-SP CCR @-SP PC
----------
14
16
RTE
RTE
--
CCR @SP+ PC @SP+

10
SLEEP SLEEP
--
Transition to powerdown state
------------
2

LDC
LDC #xx:8, CCR LDC Rs, CCR LDC @ERs, CCR LDC @(d:16, ERs), CCR LDC @(d:24, ERs), CCR LDC @ERs+, CCR
B B W W W W
2 2 4 6 10 4
#xx:8 CCR Rs8 CCR @ERs CCR @(d:16, ERs) CCR @(d:24, ERs) CCR @ERs CCR ERs32+2 ERs32 @aa:16 CCR @aa:24 CCR CCR Rd8 4 6 10 4 CCR @ERd CCR @(d:16, ERd) CCR @(d:24, ERd) ERd32-2 ERd32 CCR @ERd CCR @aa:16 CCR @aa:24 CCR#xx:8 CCR CCR#xx:8 CCR CCR#xx:8 CCR 2 PC PC+2
2 2 6 8 12 8


LDC @aa:16, CCR LDC @aa:24, CCR STC STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16, ERd) STC CCR, @(d:24, ERd) STC CCR, @-ERd
W W B W W W W 2
6 8
8 10 2 6 8 12 8
------------ ------------ ------------ ------------ ------------
STC CCR, @aa:16 STC CCR, @aa:24 ANDC ANDC #xx:8, CCR ORC ORC #xx:8, CCR
W W B B B -- 2 2 2
6 8
------------ ------------

8 10 2 2 2 2
XORC XORC #xx:8, CCR NOP NOP
------------
Rev. 3.00 Mar. 15, 2006 Page 476 of 526 REJ09B0060-0300
Appendix
8. Block Transfer Instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
@-ERn/@ERn+
Operand Size
Condition Code Operation
Mnemonic
@(d, ERn)
I
H
N
Z
V
C
EEPMOV
EEPMOV. B
--
4 if R4L 0 then repeat @R5 @R6 R5+1 R5 R6+1 R6 R4L-1 R4L until else next R4L=0
------------
8+ 4n*2
EEPMOV. W
--
4 if R4 0 then repeat @R5 @R6 R5+1 R5 R6+1 R6 R4-1 R4 until else next R4=0
------------
8+ 4n*2
Notes: 1. The number of states in cases where the instruction code and its operands are located in on-chip memory is shown here. For other cases, see appendix A.3, Number of Execution States. 2. n is the value set in register R4L or R4. (1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. (2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. (3) Retains its previous value when the result is zero; otherwise cleared to 0. (4) Set to 1 when the adjustment produces a carry; otherwise retains its previous value. (5) The number of states required for execution of an instruction that transfers data in synchronization with the E clock is variable. (6) Set to 1 when the divisor is negative; otherwise cleared to 0. (7) Set to 1 when the divisor is zero; otherwise cleared to 0. (8) Set to 1 when the quotient is negative; otherwise cleared to 0.
Rev. 3.00 Mar. 15, 2006 Page 477 of 526 REJ09B0060-0300
Advanced
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
A.2
Appendix
Table A.2
Instruction code: Instruction when most significant bit of BH is 1.
4 ORC ADD SUB Table A.2 Table A.2 (2) (2) CMP SUBX OR.B XOR.B AND.B Table A.2 (2) XORC ANDC LDC Table A.2 Table A.2 (2) (2) MOV ADDX Table A.2 (2) Table A.2 (2) 5 6 7 8 9 A B C D E F
REJ09B0060-0300
1st byte 2nd byte AH AL BH BL Instruction when most significant bit of BH is 0.
3 LDC
AL
AH
0
1
2
0
NOP
Table A.2 (2)
STC
Operation Code Map
1
Table A.2 Table A.2 Table A.2 Table A.2 (2) (2) (2) (2)
2 MOV.B
Rev. 3.00 Mar. 15, 2006 Page 478 of 526
Operation Code Map (1)
3 BLS BCC RTS BST OR BTST BOR MOV BIOR ADD ADDX CMP SUBX OR XOR AND MOV BIXOR BIAND BILD BXOR BAND BIST BLD XOR AND BSR RTE TRAPA Table A.2 (2) JMP MOV Table A.2 Table A.2 EEPMOV (2) (2) Table A.2 (3) BCS BNE BEQ BVC BPL BMI DIVXU BVS BGE BSR BLT BGT JSR BLE
4
BRA
BRN
BHI
5
MULXU
DIVXU
MULXU
6
BSET
BNOT
BCLR
7
8
9
A
B
C
D
E
F
Table A.2
Instruction code:
1st byte 2nd byte AH AL BH BL
2 LDC/STC SLEEP ADD INC ADDS MOV SHLL SHAL SHAR ROTL ROTR EXTU EXTU NEG SHLR ROTXL ROTXR NOT SHAL SHAR ROTL ROTR NEG SUB DEC DEC SUB CMP BHI BLS SUB SUB OR OR XOR XOR BCS CMP CMP BCC BNE AND AND BEQ BVC BVS BPL BMI BGE BLT BGT BLE DEC DEC EXTS EXTS INC INC INC Table A.2 Table A.2 (3) (3) 3 4 5 6 7 8 9 A B C D E F Table A.2 (3)
BH AH AL
0
1
01
MOV
0A
INC
0B
ADDS
Operation Code Map (2)
0F
DAA
10
SHLL
11
SHLR
12
ROTXL
13
ROTXR
17
NOT
1A
DEC
1B
SUBS
1F
DAS
58
BRA
BRN
79
MOV
ADD
7A
MOV
ADD
Appendix
Rev. 3.00 Mar. 15, 2006 Page 479 of 526
REJ09B0060-0300
Appendix
Table A.2
REJ09B0060-0300
Instruction code:
1st byte 2nd byte 3rd byte 4th byte AH AL BH BL CH CL DH DL
Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1.
CL 2 3 4 5 6 7 8 9 A B C D E F
AH ALBH BLCH LDC STC STC MULXS DIVXS OR BTST BOR BTST BIOR BCLR BIST BCLR BTST BOR BTST BIOR BCLR BIST BCLR BIXOR BIAND BILD BST BXOR BAND BLD BIXOR BIAND BILD BST BXOR BAND BLD XOR AND LDC LDC STC
0
1
01406
LDC STC
Rev. 3.00 Mar. 15, 2006 Page 480 of 526
Operation Code Map (3)
01C05
MULXS
01D05
DIVXS
01F06
7Cr06 * 1
7Cr07 * 1
7Dr06 * 1
BSET
BNOT
7Dr07 * 1
BSET
BNOT
7Eaa6 * 2
7Eaa7 * 2
7Faa6 * 2
BSET
BNOT
7Faa7 * 2
BSET
BNOT
Notes: 1. r is the register designation field. 2. aa is the absolute address field.
Appendix
A.3
Number of Execution States
The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. Table A.3 shows the number of states required for each cycle. The total number of states required for execution of an instruction can be calculated by the following expression:
Execution states = I x SI + J x SJ + K x SK + L x SL + M x SM + N x SN
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A.4:
I = L = 2, J = K = M = N= 0
From table A.3:
SI = 2, SL = 2
Number of states required for execution = 2 x 2 + 2 x 2 = 8 When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and on-chip RAM is used for stack area.
JSR @@ 30
From table A.4:
I = 2, J = K = 1, L=M=N=0
From table A.3:
SI = SJ = SK = 2 Number of states required for execution = 2 x 2 + 1 x 2+ 1 x 2 = 8
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Appendix
Table A.3
Number of Cycles in Each Instruction
Access Location On-Chip Memory SI SJ SK SL SM SN 1 2 or 3* -- 2 On-Chip Peripheral Module --
Execution Status (Instruction Cycle) Instruction fetch Branch address read Stack operation Byte data access Word data access Internal operation Note: *
Depends on which on-chip peripheral module is accessed. See section 22.1, Register Addresses (Address Order).
Rev. 3.00 Mar. 15, 2006 Page 482 of 526 REJ09B0060-0300
Appendix
Table A.4
Number of Cycles in Each Instruction
Instruction Fetch I 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 Stack Branch Addr. Read Operation K J Byte Data Access L Word Data Access M Internal Operation N
Instruction Mnemonic ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS ADDX ADDS #1/2/4, ERd ADDX #xx:8, Rd ADDX Rs, Rd AND AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd ANDC BAND ANDC #xx:8, CCR BAND #xx:3, Rd BAND #xx:3, @ERd BAND #xx:3, @aa:8 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8
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Appendix
Instruction Instruction Mnemonic Bcc BLT d:8 BGT d:8 BLE d:8 BRA d:16(BT d:16) BRN d:16(BF d:16) BHI d:16 BLS d:16 BCC d:16(BHS d:16) BCS d:16(BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @ERd BIAND #xx:3, @aa:8 BILD BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8 Fetch I 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 1 2 2 1 2 2 1 2 2
Branch
Stack
Byte Data Access L
Word Data Access M
Internal Operation N
Addr. Read Operation J K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2
2 2
1 1
1 1
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Appendix
Instruction Instruction Mnemonic BIOR BIOR #xx:8, Rd BIOR #xx:8, @ERd BIOR #xx:8, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8 BLD BLD #xx:3, Rd BLD #xx:3, @ERd BLD #xx:3, @aa:8 BNOT BNOT #xx:3, Rd BNOT #xx:3, @ERd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @ERd BNOT Rn, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BSET BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BSR BSR d:8 BSR d:16 BST BST #xx:3, Rd BST #xx:3, @ERd BST #xx:3, @aa:8 Fetch I 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 2 1 2 2
Branch
Stack
Byte Data Access L
Word Data Access M
Internal Operation N
Addr. Read Operation J K
1 1
2 2
1 1
1 1
2 2
2 2
1 1
2 2
2 2 1 1 2
2 2
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Appendix
Instruction Instruction Mnemonic BTST BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 CMP CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd DAA DAS DEC DAA Rd DAS Rd DEC.B Rd DEC.W #1/2, Rd DEC.L #1/2, ERd DIVXS DIVXS.B Rs, Rd DIVXS.W Rs, ERd DIVXU DIVXU.B Rs, Rd DIVXU.W Rs, ERd EEPMOV EEPMOV.B EEPMOV.W EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd Fetch I 1 2 2 1 2 2 1 2 2 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 2 2 1 1 1 1
Branch
Stack
Byte Data Access L
Word Data Access M
Internal Operation N
Addr. Read Operation J K
1 1
1 1
1 1
12 20 12 20 2n+2*
1
2n+2*1
Rev. 3.00 Mar. 15, 2006 Page 486 of 526 REJ09B0060-0300
Appendix
Instruction Instruction Mnemonic INC INC.B Rd INC.W #1/2, Rd INC.L #1/2, ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 LDC LDC #xx:8, CCR LDC Rs, CCR LDC@ERs, CCR LDC@(d:16, ERs), CCR LDC@(d:24,ERs), CCR LDC@ERs+, CCR LDC@aa:16, CCR LDC@aa:24, CCR MOV MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @Erd MOV.B Rs, @(d:16, ERd) MOV.B Rs, @(d:24, ERd) MOV.B Rs, @-ERd MOV.B Rs, @aa:8 Fetch I 1 1 1 2 2 2 2 2 2 1 1 2 3 5 2 3 4 1 1 1 2 4 1 1 2 3 1 2 4 1 1
Branch
Stack
Byte Data Access L
Word Data Access M
Internal Operation N
Addr. Read Operation J K
2 1 1 1 1 1 2 2
1 1 1 1 1 1 2
1 1 1 1 1 1 1 1 1 1 1 1 2 2
Rev. 3.00 Mar. 15, 2006 Page 487 of 526 REJ09B0060-0300
Appendix
Instruction Instruction Mnemonic MOV MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd MOV.W @(d:16,ERs), Rd MOV.W @(d:24,ERs), Rd MOV.W @ERs+, Rd MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd MOV.W Rs, @(d:16,ERd) MOV.W Rs, @(d:24,ERd) MOV MOV.W Rs, @-ERd MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 MOV.L #xx:32, ERd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16,ERs), ERd MOV.L @(d:24,ERs), ERd MOV.L @ERs+, ERd MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs,@ERd MOV.L ERs, @(d:16,ERd) MOV.L ERs, @(d:24,ERd) MOV.L ERs, @-ERd MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 MOVFPE MOVTPE MOVFPE @aa:16, Rd* MOVTPE Rs,@aa:16*
2 2
Branch
Stack
Byte Data Access L 1 1
Word Data Access M
Internal Operation N
Fetch I 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 2 2
Addr. Read Operation J K
1 1 1 1 1 1 1 1 1 1 1 1 2 2
2 2 2 2 2 2 2 2 2 2 2 2 1 1 2 2
Rev. 3.00 Mar. 15, 2006 Page 488 of 526 REJ09B0060-0300
Appendix
Instruction Instruction Mnemonic MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd MULXU MULXU.B Rs, Rd MULXU.W Rs, ERd NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOP NOT.B Rd NOT.W Rd NOT.L ERd OR OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd ORC POP ORC #xx:8, CCR POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR ROTR.B Rd ROTR.W Rd ROTR.L ERd ROTXL ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd Fetch I 2 2 1 1 1 1 1 1 1 1 1 1 1 2 1 3 2 1 1 2 1 2 1 1 1 1 1 1 1 1 1
Branch
Stack
Byte Data Access L
Word Data Access M
Internal Operation N 12 20 12 20
Addr. Read Operation J K
1 2 1 2
2 2 2 2
Rev. 3.00 Mar. 15, 2006 Page 489 of 526 REJ09B0060-0300
Appendix
Instruction Instruction Mnemonic ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd RTE RTS SHAL RTE RTS SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR SHLR.B Rd SHLR.W Rd SHLR.L ERd SLEEP STC SLEEP STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16,ERd) STC CCR, @(d:24,ERd) STC CCR,@-ERd STC CCR, @aa:16 STC CCR, @aa:24 SUB SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd SUB.L ERs, ERd SUBS SUBS #1/2/4, ERd Fetch I 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 5 2 3 4 1 2 1 3 1 1
Branch
Stack
Byte Data Access L
Word Data Access M
Internal Operation N
Addr. Read Operation J K
2 1
2 2
1 1 1 1 1 1 2
Rev. 3.00 Mar. 15, 2006 Page 490 of 526 REJ09B0060-0300
Appendix
Instruction Instruction Mnemonic SUBX SUBX #xx:8, Rd SUBX. Rs, Rd TRAPA XOR TRAPA #xx:2 XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd XORC XORC #xx:8, CCR Fetch I 1 1 2 1 1 2 1 3 2 1
Branch
Stack
Byte Data Access L
Word Data Access M
Internal Operation N
Addr. Read Operation J K
1
2
4
Notes: 1. n: Specified value in R4L and R4. The source and destination operands are accessed n+1 times respectively. 2. Cannot be used in this LSI.
Rev. 3.00 Mar. 15, 2006 Page 491 of 526 REJ09B0060-0300
Appendix
A.4
Combinations of Instructions and Addressing Modes Combinations of Instructions and Addressing Modes
Addressing Mode
@ERn+/@ERn
Table A.5
@(d:16.ERn)
@(d:24.ERn)
@(d:8.PC)
Functions
Instructions
@ERn
@(d:16.PC)
@@aa:8
@aa:16
@aa:24
@aa:8
#xx
Rn
Data transfer instructions
MOV POP, PUSH MOVFPE, MOVTPE
BWL BWL BWL BWL BWL BWL -- -- -- -- -- -- -- -- -- -- -- --
B -- --
BWL BWL -- -- -- --
-- -- --
-- -- --
-- -- --
-- WL --
Arithmetic operations
ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, MULXS, DIVXU, DIVXS NEG EXTU, EXTS
BWL BWL WL B -- -- -- -- BWL B L BWL B BW
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- B -- B
BWL WL BWL BWL BWL B -- -- -- -- -- -- B B --
-- -- -- -- -- B --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- W W --
-- -- -- -- -- -- -- -- -- -- -- -- W W --
-- -- -- -- -- B -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- W W --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- --
Logical operations
AND, OR, XOR NOT
Shift operations Bit manipulations Branching instructions BCC, BSR JMP, JSR RTS System control instructions TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP Block data transfer instructions
-- -- -- -- W W --
-- -- -- -- W W --
-- -- -- -- W W -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- --
-- --
-- --
-- --
-- --
-- --
-- --
-- --
-- --
-- --
-- --
-- --
-- --
-- -- BW
Rev. 3.00 Mar. 15, 2006 Page 492 of 526 REJ09B0060-0300
--
Appendix
B.
B.1
I/O Ports
I/O Port Block Diagrams
RES goes low in a reset, and SBY goes low at reset and in standby mode.
Internal data bus PUCR RES SBY Pull-up MOS
PMR
PDR
PCR
IRQ TRGV [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.1 Port 1 Block Diagram (P17)
Rev. 3.00 Mar. 15, 2006 Page 493 of 526 REJ09B0060-0300
Appendix
Internal data bus
RES PUCR
SBY
Pull-up MOS
PMR
PDR
PCR
IRQ [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.2 Port 1 Block Diagram (P14, P16)
Rev. 3.00 Mar. 15, 2006 Page 494 of 526 REJ09B0060-0300
Appendix
Internal data bus
RES
SBY Pull-up MOS
PUCR PMR
PDR PCR
IRQ TMIB1 [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.3 Port 1 Block Diagram (P15)
Internal data bus PUCR Pull-up MOS
RES
SBY
PDR PCR
[Legend] PUCR: Port pull-up control register PDR: Port data register PCR: Port control register
Figure B.4 Port 1 Block Diagram (P12)
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Appendix
Internal data bus
RES
SBY
PUCR Pull-up MOS PMR
PDR
PCR
14-bit PWM PWM [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.5 Port 1 Block Diagram (P11)
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Appendix
Internal data bus
RES
SBY
PUCR Pull-up MOS PMR
PDR
PCR
RTC TMOW [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.6 Port 1 Block Diagram (P10)
Internal data bus
SBY
PMR
PDR
PCR
[Legend] PUCR: Port pull-up control register PDR: Port data register PCR: Port control register
Figure B.7 Port 2 Block Diagram (P24, P23)
Rev. 3.00 Mar. 15, 2006 Page 497 of 526 REJ09B0060-0300
Appendix
Internal data bus
SBY
PMR
PDR
PCR
SCI3 TxD [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.8 Port 2 Block Diagram (P22)
SBY Internal data bus
PDR
PCR
SCI3 RE RxD [Legend] PDR: Port data register PCR: Port control register
Figure B.9 Port 2 Block Diagram (P21)
Rev. 3.00 Mar. 15, 2006 Page 498 of 526 REJ09B0060-0300
Appendix
SCI3 SCKIE SCKOE Internal data bus PDR
SBY
PCR
SCKO SCKI [Legend] PDR: Port data register PCR: Port control register
Figure B.10 Port 2 Block Diagram (P20)
Internal data bus
SBY
PDR
PCR
[Legend] PDR: Port data register PCR: Port control register
Figure B.11 Port 3 Block Diagram (P37 to P30)
Rev. 3.00 Mar. 15, 2006 Page 499 of 526 REJ09B0060-0300
Appendix
Internal data bus
SBY
PMR
PDR
PCR
IIC2 ICE SDAO/SCLO SDAI/SCLI
[Legend] PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.12 Port 5 Block Diagram (P57, P56)
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Appendix
Internal data bus RES SBY
PUCR PMR
Pull-up MOS
PDR PCR
ADTRG WKP5 [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.13 Port 5 Block Diagram (P55)
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Appendix
Internal data bus
RES
SBY
PUCR PMR
Pull-up MOS
PDR PCR
WKP [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.14 Port 5 Block Diagram (P54 to P50)
Rev. 3.00 Mar. 15, 2006 Page 502 of 526 REJ09B0060-0300
Appendix
Internal data bus Timer Z Output control signals A to D
SBY
PDR
PCR
FTIOA to FTIOD
[Legend] PDR: Port data register PCR: Port control register
Figure B.15 Port 6 Block Diagram (P67 to P60)
Internal data bus
SBY
PDR
PCR
[Legend] PDR: Port data register PCR: Port control register
Figure B.16 Port 7 Block Diagram (P77)
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Appendix
Internal data bus Timer V OS3 OS2 OS1 OS0 PDR SBY
PCR
TMOV [Legend] PDR: Port data register PCR: Port control register
Figure B.17 Port 7 Block Diagram (P76)
Internal data bus
SBY
PDR
PCR
Timer V TMCIV [Legend] PDR: Port data register PCR: Port control register
Figure B.18 Port 7 Block Diagram (P75)
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Appendix
Internal data bus
SBY
PDR
PCR
Timer V TMRIV [Legend] PDR: Port data register PCR: Port control register
Figure B.19 Port 7 Block Diagram (P74)
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Appendix
Internal data bus
SBY
PMR
PDR
PCR
SCI3_2 TxD [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.20 Port 7 Block Diagram (P72)
Internal data bus SBY
PDR
PCR
SCI3_2 RE RxD [Legend] PDR: Port data register PCR: Port control register
Figure B.21 Port 7 Block Diagram (P71)
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Appendix
SBY SCI3_2 SCKIE SCKOE Internal data bus PDR
PCR
SCKO SCKI [Legend] PDR: Port data register PCR: Port control register
Figure B.22 Port 7 Block Diagram (P70)
Internal data bus SBY
PDR PCR
[Legend] PDR: Port data register PCR: Port control register
Figure B.23 Port 8 Block Diagram (P87 to P85)
Rev. 3.00 Mar. 15, 2006 Page 507 of 526 REJ09B0060-0300
Appendix
Internal data bus Timer W Output control signals A to D
SBY
PDR
PCR
FTIOA to FTIOD
[Legend] PDR: Port data register PCR: Port control register
Figure B.24 Port 8 Block Diagram (P84 to P81)
Internal data bus SBY
PDR PCR
Timer W FTCI [Legend] PDR: Port data register PCR: Port control register
Figure B.25 Port8 Block Diagram (P80)
Rev. 3.00 Mar. 15, 2006 Page 508 of 526 REJ09B0060-0300
Appendix
Internal data bus
PDR PCR
[Legend] PDR: Port data register PCR: Port control register
Figure B.26 Port 9 Block Diagram (P97 to P93)
Internal data bus
SBY
SMCR
PDR
PCR
SCI3_3 TxD [Legend] SMCR: Serial module control register PDR: Port data register PCR: Port control register
Figure B.27 Port 9 Block Diagram (P92)
Rev. 3.00 Mar. 15, 2006 Page 509 of 526 REJ09B0060-0300
Appendix
SBY Internal data bus
PDR
PCR
SCI3_3 RE RxD [Legend] PDR: Port data register PCR: Port control register
Figure B.28 Port 9 Block Diagram (P91)
SBY SCI3_3 SCKIE SCKOE Internal data bus PDR
PCR
SCKO SCKI [Legend] PDR: Port data register PCR: Port control register
Figure B.29 Port 9 Block Diagram (P90)
Rev. 3.00 Mar. 15, 2006 Page 510 of 526 REJ09B0060-0300
Appendix
Internal data bus
A/D converter DEC CH3 to CH0 VIN
Figure B.30 Port B Block Diagram (PB7 to PB0) B.2
Port P17 to P14, P12 to P10 P24 to P20 P37 to P30 P57 to P50 P67 to P60 P76 to P74, P72 to P70 P87 to P80 P97 to P90 PB7 to PB0 Note: *
Port States in Each Operating Mode
Reset High impedance High impedance High impedance High impedance High impedance High impedance High impedance High impedance High impedance Sleep Retained Retained Retained Retained Retained Retained Retained Retained High impedance Subsleep Retained Retained Retained Retained Retained Retained Retained Retained High impedance Standby Subactive Active Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning High impedance
High Functioning impedance* High impedance High impedance Functioning Functioning
High Functioning impedance* High impedance High impedance High impedance High impedance High impedance Functioning Functioning Functioning Functioning High impedance
High level output when the pull-up MOS is in on state.
Rev. 3.00 Mar. 15, 2006 Page 511 of 526 REJ09B0060-0300
Appendix
C.
Product Code Lineup
Product Code Model Marking Package (Package Code)
QFP-80 (FP-80A)
Product Classification
H8/36049 Flash memory Product with HD64F36049GH HD64F36049GH version POR & LVDC Standard product
HD64F36049H HD64F36049H
Masked ROM Product with HD64336049GH HD64336049(***)GH version POR & LVDC Standard product
HD64336049H HD64336049(***)H
H8/36048 Masked ROM Product with HD64336048GH HD64336048(***)GH version POR & LVDC Standard product
HD64336048H HD64336048(***)H
H8/36047 Masked ROM Product with HD64336047GH HD64336047(***)GH version POR & LVDC Standard product [Legend] (***): ROM code POR & LVDC: Power-on reset and low-voltage detection circuits
HD64336047H HD64336047(***)H
Rev. 3.00 Mar. 15, 2006 Page 512 of 526 REJ09B0060-0300
Appendix
D.
Package Dimensions
The package dimensions that are shown in the Renesas Semiconductor Packages Data Book have priority.
17.2 0.3 14 60 61
17.2 0.3
Unit: mm
41 40
80 1 *0.32 0.08 0.30 0.06 0.12 0.83 20 M
21
0.65 3.05 Max
*0.17 0.05
0.15 0.04
2.70
1.6
+0.15 0.10 -0.10
0 - 8 0.8 0.3
0.10
*Dimension including the plating thickness Base material dimension
Package Code JEDEC JEITA Mass (reference value)
FP-80A -- Conforms 1.2 g
Figure D.1 FP-80A Package Dimensions
Rev. 3.00 Mar. 15, 2006 Page 513 of 526 REJ09B0060-0300
Appendix
Rev. 3.00 Mar. 15, 2006 Page 514 of 526 REJ09B0060-0300
Main Revisions and Additions in this Edition
Item Preface Notes Page Revision (See Manual for Details) vii Added When using an on-chip emulator (E7 or E8) for H8/36049 Group program development and debugging, the following restrictions must be noted. 1. The NMI pin is reserved for the E7 or E8, and cannot be used. 2. Pins P85, P86, and P87 cannot be used. 3. Area H'FFF780 to H'FFFB7F must on no account be accessed. 4. When the E7 or E8 is used, address breaks can be set as either available to the user or for use by the E7 or E8. If address breaks are set as being used by the E7 or E8, the address break control registers must not be accessed. 5. When the E7 or E8 is used, NMI is an input/output pin (open-drain in output mode), P85 and P87 are input pins, and P86 is an output pin. 6.1.1 System Control Register 1 (SYSCR1) 76 Amended Bit Bit Name Description 3 NESEL Noise Elimination Sampling Frequency Select .... This bit selects the sampling frequency of the oscillator clock when the watch clock signal (W) is sampled. When OSC = 4 to 20 MHz, clear NESEL to 0.
Rev. 3.00 Mar. 15, 2006 Page 515 of 526 REJ09B0060-0300
Item
Page Revision (See Manual for Details) Amended Example: Direct transition time = (2 + 1) x tosc + 16 x 8 tw = 3 tosc + 128 tw (when the CPU operating clock of osc w/8 is selected)
6.4.1 Direct Transition from Active 86 Mode to Subactive Mode
6.4.2 Direct Transition from Subactive Mode to Active Mode
87
Amended Example: Direct transition time = (2 + 1) x 8 tw + (8192 + 16) x tosc = 24 tw + 8208 tosc (when the CPU operating clock of w/8 osc and a waiting time of 8192 states are selected)
Section 8 RAM
109
Added Note: * When the E7 or E8 is used, area H'FFF780 to H'FFFB7F must not be accessed.
9.7.3 Pin Functions * P84/FTIOD pin
139
Amended Register Bit Name TMRW PWMD
9.7.3 Pin Functions * P83/FTIOC pin
140
Amended Register Bit Name TMRW PWMC
9.7.3 Pin Functions * P82/FTIOB pin
140
Amended Register Bit Name TMRW PWMB
Rev. 3.00 Mar. 15, 2006 Page 516 of 526 REJ09B0060-0300
Item 14.3.2 Timer Mode Register (TMDR)
Page Revision (See Manual for Details) 221 Amended Bit Bit Name 0 SYNC Description Timer Synchronization 0: TCNT_1 and TCNT_0 operate as a different timer 1: TCNT_1 and TCNT_0 are synchronized TCNT_1 and TCNT_0 can be pre-set or cleared synchronously
14.3.7 Timer Counter (TCNT)
228
....The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. TCNT is initialized to H'0000. Amended
Counter cleared by FTIOB input (falling edge)
Figure 14.17 Example of Input Capture Operation
245
Time
14.4.4 Synchronous Operation
248
Added Figure 14.20 shows an example of synchronous operation. In this example, .... set for the channel 1 counter clearing source. In addition, the same input clock has been set as the counter input clock for channel 0 and channel 1. Two-phase PWM waveforms are....
Rev. 3.00 Mar. 15, 2006 Page 517 of 526 REJ09B0060-0300
Item Figure 14.44 Example of Output Disable Timing of Timer Z by Writing to TOER
Page Revision (See Manual for Details) 276 Amended
T1 T2
Address bus
TOER address
TOER
Timer Z output pin
Timer output I/O port
I/O port
Timer Z output
Figure 14.45 Example of Output Disable Timing of Timer Z by External Trigger
277
Amended
WKP4
TOER
N
H'FF
Timer Z output pin
Timer Z output
I/O port
15.2.1 Timer Control/Status Register WD (TCSRWD
290
Amended Bit 4 Bit Name TCSRWE Description Timer Control/Status Register WD Write Enable The WDON and WRST bits can be written when the TCSRWE bit is set to 1. When writing data to this bit, the value for bit 5 must be 0.
Rev. 3.00 Mar. 15, 2006 Page 518 of 526 REJ09B0060-0300
Item 18.3.5 I C Bus Status Register (ICSR)
2
Page Revision (See Manual for Details) 353 Amended Bit 3 Bit Name Description STOP Stop Condition Detection Flag [Setting conditions] * In master mode, when a stop condition is detected after frame transfer In slave mode, when a stop condition is detected after the general call address or the first byte slave address, next to detection of start condition, accords with the address set in SAR
*
18.7 Usage Note 19.3.1 A/D Data Registers A to D (ADDRA to ADDRD)
375 380
Added Amended .... The temporary register contents are transferred from the ADDR when the upper byte data is read. Therefore, byte access to ADDR should be done by reading the upper byte first then the lower one. Word access is also possible. ADDR is initialized to H'0000. Amended
Figure 20.1 Block Diagram of 392 Power-On Reset Circuit and LowVoltage Detection Circuit
RES
CRES
Table 23.2 DC Characteristics (1) 431, 450 Table 23.11 DC Characteristics (1)
Amended
Mode Active mode 1 Active mode 2 Sleep mode 1 Sleep mode 2 VCC RES Pin Internal State VCC Operates Operates (OSC/64) Only timers operate Only timers operate (OSC/64)
Rev. 3.00 Mar. 15, 2006 Page 519 of 526 REJ09B0060-0300
Item Figure 23.4 I C Bus Interface Input/Output Timing
2
Page Revision (See Manual for Details) 460 Deleted
SDA tBUF
VIH VIL tSTAH tSCLH
SCL P* S* tSf tSCLL tSCL
tSr
Table A.1 Instruction Set 2. Arithmetic Instructions
467
Amended
No. of States*1
Operand Size
I
H
N
Z
V
C
DAA
DAA Rd
B--*
Normal
2
Mnemonic
*
Rev. 3.00 Mar. 15, 2006 Page 520 of 526 REJ09B0060-0300
Advanced
Condition Code
Index
Numerics
14-bit PWM ............................................ 295
D
Data reading procedure ........................... 158 Data transfer instructions .......................... 19
A
A/D converter ......................................... 377 Absolute address....................................... 29 Acknowledge .......................................... 358 Address break ........................................... 63 Addressing modes..................................... 28 Arithmetic operations instructions............ 20 Asynchronous mode ............................... 318 Auto-reload timer operation ................... 164
E
Effective address....................................... 31 Effective address extension....................... 27 Erase/erase-verify ................................... 103 Erasing units ............................................. 90 Error protection....................................... 105 Event counter operation .......................... 164 Exception handling ................................... 43
B
Bit manipulation instructions.................... 23 Bit rate .................................................... 309 Bit synchronous circuit ........................... 374 Block data transfer instructions ................ 26 Boot mode ................................................ 95 Boot program............................................ 95 Branch instructions ................................... 25 Break....................................................... 339 Buffer operation...................................... 268
F
Flash memory ........................................... 89 Framing error .......................................... 322
G
General registers ....................................... 12
H
Hardware protection................................ 105
C
Clock pulse generators.............................. 69 Clock synchronous serial format ............ 366 Clocked synchronous mode .................... 326 Combinations of instructions and addressing modes.................................... 492 Complementary PWM mode .................. 258 Condition field.......................................... 27 Condition-code register (CCR)................. 13 CPU ............................................................ 9
I
I/O Port block diagrams .......................... 493 I/O ports .................................................. 111 I2C Bus format ........................................ 357 I2C bus interface 2 (IIC2)........................ 341 Immediate ................................................. 30 Initial setting procedure .......................... 157 Input capture function ............................. 244 Instruction list ......................................... 463
Rev. 3.00 Mar. 15, 2006 Page 521 of 526 REJ09B0060-0300
Instruction set ........................................... 18 Internal interrupts ..................................... 57 Internal power supply step-down circuit...................................................... 401 Interrupt mask bit (I)................................. 13 Interrupt response tme .............................. 59 Interval timer operation .......................... 163 IRQ3 to IRQ0 interrupts ........................... 55
O
On-board programming modes ................. 95 Operation code map ................................ 478 Operation field .......................................... 27 Overrun error .......................................... 322
P
Package ....................................................... 2 Package dimensions................................ 513 Parity error .............................................. 322 Pin arrangement .......................................... 4 Power-down modes................................... 75 Power-down states .................................. 106 power-on reset......................................... 391 Power-on reset circuit ............................. 396 Prescaler S ................................................ 73 Prescaler W ............................................... 73 Product code lineup ................................ 512 Program counter (PC) ............................... 13 Program/program-verify ......................... 100 Program-counter relative .......................... 30 Programmer mode................................... 106 Programming units.................................... 90 Programming/erasing in user program mode ......................................................... 98 PWM mode............................................. 248 PWM operation....................................... 199
L
Large current ports...................................... 2 Logic operations instructions.................... 22 low-voltage detection circuit .................. 391 LVDI ...................................................... 398 LVDI (interrupt by low voltage detect) circuit...................................................... 398 LVDR ..................................................... 397 LVDR (reset by low voltage detect) circuit...................................................... 397
M
Mark state ............................................... 339 Memory indirect ....................................... 30 Memory map ............................................ 10 Module standby function .......................... 87 Multiprocessor communication function................................................... 332
R N
NMI interrupt............................................ 55 Noise canceler ........................................ 368 Noise canceller ....................................... 301 Number of execution states .................... 481 Realtime clock (RTC) ............................. 147 Register addresses................................... 404 Register bits ............................................ 411 Register direct ........................................... 28 Register field............................................. 27 Register indirect........................................ 28
Rev. 3.00 Mar. 15, 2006 Page 522 of of 526 REJ09B0060-0300
Register indirect with displacement.......... 29 Register indirect with post-increment....... 29 Register indirect with pre-decrement........ 29 Register settings...................................... 297 Register states in each operating mode ....................................................... 417 Registers ABRKCR................ 64, 66, 409, 415, 420 ABRKSR ...................... 66, 409, 415, 420 ADCR ......................... 382, 408, 414, 420 ADCSR....................... 381, 408, 414, 420 ADDRA ...................... 380, 408, 414, 419 ADDRB ...................... 380, 408, 414, 419 ADDRC ...................... 380, 408, 414, 419 ADDRD ...................... 380, 408, 414, 420 BARE ........................... 66, 409, 415, 420 BARH ........................... 66, 409, 415, 420 BARL ........................... 66, 409, 415, 420 BDRH ........................... 66, 409, 415, 420 BDRL ........................... 66, 409, 415, 420 BRR ............................ 309, 407, 414, 419 EBR1 ............................ 93, 407, 414, 419 FENR............................ 94, 407, 414, 419 FLMCR1....................... 91, 407, 414, 419 FLMCR2....................... 92, 407, 414, 419 FLPWCR ...................... 94, 407, 414, 419 GRA........................... 193, 228, 404, 407, .................................... 411, 413, 417, 419 GRB........................... 193, 228, 404, 407, .................................... 411, 413, 417, 419 GRC........................... 193, 228, 404, 407, .................................... 411, 413, 417, 419 GRD........................... 193, 228, 404, 407, .................................... 411, 414, 417, 419 ICCR1......................... 344, 406, 413, 418 ICCR2......................... 347, 406, 413, 418 ICDRR........................ 356, 406, 413, 418 ICDRS ................................................ 356 ICDRT ........................ 356, 406, 413, 418 ICIER.......................... 350, 406, 413, 418
ICMR .......................... 348, 406, 413, 418 ICSR.................... 352, 406, 413, 418, 518 IEGR1 ........................... 47, 410, 416, 421 IEGR2 ........................... 48, 410, 416, 421 IENR1 ........................... 49, 410, 416, 421 IENR2 ........................... 50, 410, 416, 421 IRR1.............................. 50, 410, 416, 421 IRR2.............................. 52, 410, 416, 421 IWPR ............................ 53, 410, 416, 421 LVDCR....................... 393, 406, 412, 418 LVDSR ....................... 395, 406, 412, 418 MSTCR1....................... 79, 410, 416, 421 MSTCR2....................... 80, 410, 416, 421 PCR1........................... 113, 410, 415, 420 PCR2........................... 117, 410, 415, 421 PCR3........................... 120, 410, 415, 421 PCR5........................... 125, 410, 415, 421 PCR6........................... 129, 410, 416, 421 PCR7........................... 134, 410, 416, 421 PCR8........................... 138, 410, 416, 421 PCR9........................... 142, 410, 416, 421 PDR1........................... 113, 409, 415, 420 PDR2........................... 117, 409, 415, 420 PDR3........................... 121, 409, 415, 420 PDR5........................... 125, 409, 415, 420 PDR6........................... 130, 409, 415, 420 PDR7........................... 135, 409, 415, 420 PDR8........................... 138, 409, 415, 420 PDR9........................... 142, 409, 415, 420 PDRB .......................... 145, 409, 415, 420 PMR1 .......................... 112, 409, 415, 420 PMR3 .......................... 118, 410, 415, 420 PMR5 .......................... 124, 409, 415, 420 POCR .......................... 235, 404, 411, 417 PUCR1 ........................ 114, 409, 415, 420 PUCR5 ........................ 126, 409, 415, 420 PWCR ......................... 296, 408, 415, 420 PWDRL ...................... 297, 408, 415, 420 PWDRU ...................... 297, 408, 415, 420 RDR ............................ 303, 408, 414, 419
Rev. 3.00 Mar. 15, 2006 Page 523 of 526 REJ09B0060-0300
RHRDR .......................151, 405, 412, 418 RMINDR .....................150, 405, 412, 418 RSECDR......................149, 405, 412, 418 RSR .................................................... 303 RTCCR1 ......................153, 405, 412, 418 RTCCR2 ......................155, 406, 412, 418 RTCCSR......................156, 406, 412, 418 RWKDR ......................152, 405, 412, 418 SAR .............................355, 406, 413, 418 SCR3 ...........................306, 408, 414, 419 SMCR..........................301, 404, 411, 417 SMR.............................304, 407, 414, 419 SSR..............................307, 408, 414, 419 SYSCR1 ........................76, 410, 416, 421 SYSCR2 ........................77, 410, 416, 421 TCB1 ...........................163, 406, 413, 418 TCNT..........................192, 228, 404, 407, .....................................411, 413, 417, 419 TCNTV........................167, 407, 414, 419 TCORA .......................168, 407, 414, 419 TCORB........................168, 407, 414, 419 TCR .............................229, 404, 411, 417 TCRV0 ........................169, 407, 414, 419 TCRV1 ........................172, 407, 414, 419 TCRW .........................186, 407, 413, 419 TCSRV ........................170, 407, 414, 419 TCSRWD ....................290, 408, 415, 420 TCWD .........................292, 408, 415, 420 TDR .............................304, 408, 414, 419 TFCR ...........................223, 405, 412, 418 TIER ............................234, 404, 411, 417 TIERW ........................187, 407, 413, 419 TIOR0..........................189, 407, 413, 419 TIOR1..........................191, 407, 413, 419 TIORA.........................230, 404, 411, 417 TIORC .........................231, 404, 411, 417 TLB1 ...........................163, 406, 413, 418 TMB1 ..........................162, 406, 413, 418 TMDR .........................221, 405, 412, 418 TMRW.........................185, 407, 413, 419
Rev. 3.00 Mar. 15, 2006 Page 524 of of 526 REJ09B0060-0300
TMWD........................ 292, 408, 415, 420 TOCR.......................... 227, 405, 412, 418 TOER.......................... 225, 405, 412, 418 TPMR ......................... 222, 405, 412, 418 TSR ............................. 232, 404, 411, 417 TSRW ......................... 188, 407, 413, 419 TSTR........................... 220, 405, 412, 418 Reset exception handling .......................... 54 Reset synchronous PWM mode .............. 254
S
Sample-and-hold circuit.......................... 385 Scan mode............................................... 384 Serial communication interface 3 (SCI3) ..................................................... 299 Shift instructions ....................................... 22 Single mode ............................................ 384 Slave address .......................................... 358 Sleep mode................................................ 84 Software protection................................. 105 Stack pointer (SP) ..................................... 12 Stack status ............................................... 57 Standby mode ........................................... 84 Start condition......................................... 358 Stop condition ......................................... 358 Subactive mode......................................... 85 Subclock generator ................................... 72 Subsleep mode .......................................... 85 Synchronous operation............................ 247 System clock generator ............................. 70 System control instructions....................... 26
T
Timer B1................................................. 161 Timer V................................................... 165 Timer W.................................................. 181 Timer Z ................................................... 213 Transfer rate............................................ 346
Trap instruction......................................... 43
W
Watchdog timer....................................... 289 Waveform output .................................... 298 Waveform output by compare match...... 241 WKP5 to WKP0 interrupts ....................... 56
V
Vector address .......................................... 44
Rev. 3.00 Mar. 15, 2006 Page 525 of 526 REJ09B0060-0300
Rev. 3.00 Mar. 15, 2006 Page 526 of of 526 REJ09B0060-0300
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/36049 Group
Publication Date: Rev.1.00, Aug. 28, 2003 Rev.3.00, Mar. 15, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.
2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
http://www.renesas.com
Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510
Colophon 6.0
H8/36049 Group Hardware Manual


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